Aug_EDFA_Digital

edfas.org 1 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 3 DEPARTMENTS Evaluation of a Co-simulation Approach for Functional Verification of Analog and Mixed Signal Devices Mathias Heitauer and Martin Versen A co-simulation technique using MATLAB/Simulink and Cadence is applied to the development process for a mixed-signal ASIC. Author Guidelines Author guidelines and a sample article are available at edfas. org. Potential authors should consult the guidelines for useful information prior to manuscript preparation. 4 8 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS AUGUST 2021 | VOLUME 23 | ISSUE 3 edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS 2 GUEST EDITORIAL Ravi Mahajan 34 SPECIAL ISTFA PREVIEW Susan L i 37 ISTFA EXHIBITORS LIST 38 2021 PHOTO CONTEST 39 2021 VIDEO CONTEST 41 EDUCATION NEWS Bhanu P. Sood 42 DIRECTORY OF FA PROVIDERS R osalinda Ring 43 FIB SEMWRAP UP Nicholas Anton iou 44 TRAINING CALENDAR Rosalinda R ing 46 LITERATURE REVIEW Michael R. B ruce 48 PRODUCT NEWS Ted Kolasa 51 GUEST COLUMNIST Keith Serrels 52 ADVERTISERS INDEX The Threat of Malicious Circuit-board Alteration: Attack Taxonomy and Examples Samuel H. Russ This article reviews possible ways that attacks on circuit boards can occur and shows examples of what an attack might look like. 13 For the digital edition, log in to edfas.org , click on the “News/Magazines” tab, and select “EDFA Magazine.” Triboelectric Charging Damage in Silicon- on-insulator Devices Paiboon Tangyunyong A look at distinct characteristics that are typical of damage incurred by triboelectric charging and discharging on silicon-on-insulator devices. 8 4 13 24 Machine Learning for Time-resolved Emission: Image Resolution Enhancement Samuel Chef, Chung Tah Chua, and Chee Lip Gan Recent work shows that time-resolved photo emission detection methods, especially the single-point scanner- based ones, bring valuable capabilities to the study of the latest devices. 24 ABOUT THE COVER “NanoNova.” Shows the first step in the creation of a 400 µm square hole, 10 µm deep in the center of a 15 mm x 15 mm bulk silicon die. The initial hole was created by a laser and later followed by gallium FIB for final polishing. Photo by Kevin Awai, Raytheon Technologies, False Color Images, 2020 EDFAS Photo Contest.