May_EDFA_Digital

edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 2 8 that carry the assets of the chip. Reverse engineering ana- lyzes the internal structure and connections for extracting the netlist and functionality of different IPs integrated into the advanced packaging. Although reverse engineering is a labor-intensive and time-consuming task, the netlist, functionality, security implementations, and asset loca- tion are exposed once completed. Potential adversaries such as untrusted foundry, OSAT, and reverse engineering entities have access to state-of-the-art failure analysis tools, which are also widely used in reverse engineering. Recent automation in sample preparation, imaging, and netlist extraction tools has greatly reduced the attacker’s effort in labor and time cost. [1] However, full-blown reverse engineering is not the only method for localizing the POI. An adversary without reverse engineering capability, such as end-users, can initiate partial reverse engineering by analyzing publicly availabledocuments andPEA. For example, differentiating between sequential or combinational circuit, [16] localizing cache, ARM cores, BUS, neural networks, AES core loca- tions, [6,18] is possible through simplePEA if theyhaveaccess to a photonic emissionmicroscope. Thereafter, a suitable optical attack can be used for asset extraction. SECURITY THREATS OF OPTICAL ATTACK FOR DIFFERENT PACKAGING As packaging is becomingmore complicated and used in industries where durability is crucial, it is becoming more necessary to identify defects. However, it is now getting more complex as the faults are smaller and more difficult to locate. Smaller dimensions and emerging materials areheading intohigh-valuepackaging. This fuels the need for better consistency standards for inspection. To detect objects such as mold and underfill voids, TSVs, redistribution layer (RDL) and bump defects, and foreign materials, high-resolution x-ray imaging and automated optical inspection have made great strides. In today’s advancedpackaging, the variousmaterial interfacesmake in-line defect identification critical for cost-effective, high- quality, and in-spec semiconductor products. In packag- ing, optical testing has been used for years. Optical testing is used to detect any apparent flaws or suspected latent defects that may possibly have an effect on yield. State- of-the-art nondestructive testing (NDT) techniques are used for integrated circuit (IC) packaging assessment. The inspection of 3D packaging poses very severe problems because of themultilayer nature of 3D packaging and the dramatic rise in the package’s number of components. Delamination, scratches, misalignment, void in bumps, cracks in the substrate, delamination, and void inunderfill, or void and delamination in through-silicon, are themost common defect types of 3Dpackaging and all the possible defect locations are shown in Fig.5. The confidentiality and integrity of the sensitive information protected by the security architecture are considered violated if the assets are vulnerable to optical attacks. In advanced packaged dies, security mesh is placed at the front side of the die to safeguard the sensi- tive information in the device. Moreover, a large number of interconnecting metal layers at frontside makes tracking the transistor activity impractical. However, due to the absence of any protection mechanism and metal layers, raiding the exposed silicon chip can easily be carried out from the chip’s backside. In a DIP or BGA packaged chip, the packaging polymer or ceramic prevents access to the backside of the chip, and also, the presence of a heat sink copper shield makes the sample preparation (wet etching or mechanical polishing) a little challenging. The difference between the access from the backside and front side is shown in Fig. 6. The substrate of the flip-chip is generally covered with a metallic lid that can be easily removed to expose the silicon die with minimal effort. In advanced packaging like interposer and 3D type packag- ing for heterogeneous and homogeneous integration, the covering mechanis m remains the same. However, more I/O features have be en added in the advanced packaging, which will make it more vulnerable to the optical attack. Although the sample preparation for advance packaged ICs is a bit complex, after it is de-packaged properly, it will expose more information. For interposer packaging, chips are kept in a flip-chip orientation for high band- width connectivity using TSVs, making it vulnerable to a backside optical attack. Similarly, in 3D packaging, chips are stacked together and connected using TSVs for high bandwidth connectivity and small space consumption in a flip-chip orientation. Although the 3Dpackaging ismore complicated than interposer packaging, careful sample preparationwill expose the last stacked chip for the optical attack, giving the next stage information for the further careful de-packaging process. Fig. 5 Potential defect locations in advanced IC packaging. (continued on page 10)