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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 2 4 EDFAAO (2021) 2:4-11 1537-0755/$19.00 ©ASM International ® SECURITY ASSESSMENT OF IC PACKAGING AGAINST OPTICAL ATTACKS Chengjie Xi, Aslam A. Khan, M. Tanjidur Rahman, and Navid Asadizanjani Florida Institute for Cybersecurity Research, University of Florida, Gainesville chengjiexi@ufl.edu INTRODUCTION Traditional integrated circuit (IC) packaging, in addi- tion to connecting the chip to board level, provides an enclosure to prevent the die from corrosion and better heat dissipation. However, today’s advanced packaging is integral to the device’s performance. Advanced packaging suchas system-on-chip (SOC), has facilitated the evolution of ubiquitous modern-day electronics targeted toward a range of applications including internet-of-things (IoT), automotive, financial, medical, and space exploration. Although suchadvancements in thepackagingprocess are indisputable, the ICpackaging’s security assurancehas not kept up pace. Although advanced packaging can prevent adversaries from accessing internal design information without expensive and labor-intensivepackagedelayering and sample preparation capabilities, well-resourced enti- tiesmay have greater access to a chip’s information. These integrity problems break down into physical, chemical, and electrical concerns and can pose a threat to the secu- rity and reliability of wafers and chip packaging. Modern ICs consist of billions of transistors, several intellectual property (IP) cores, complex on-chip busses, and proto- cols tomeet the current, all-encompassing technological demands. For instance, the new 10 nm FinFET A11 bionic chip has approximately four billion transistors. Due to the sheer complexity of the designs, chips are subject to rigor- ous testing and physical inspection procedures for detec- tion of manufacturing and packaging defects. [1] Optical debugging techniques are developed as fault localization and defect characterization steps in the failure analysis (FA) process. Photon emission analysis (PEA), picosecond imaging circuit analysis (PICA), laser-voltageprobing (LVP), laser voltage imaging (LVI), and laser fault injection (LFI), arewidely used optical FA techniques. Thesemethods are based on thewell-known principle of silicon transparency to near-infrared (NIR) photons. Therefore, the approaches mentioned above can localize the failure through run- timemonitoring of the device. A “malevolent genius” can use the same methods for localizing and probing device assets. [2–6] In addition, the silicon substrate has no protec- tion against active or passive photon inspection. Thus, such uncovered silicon can be an easy target for an attack- er to acquire access to the on-chip assets. Furthermore, higher I/O pin counts and compact design requirements increased the adoption of flip-chip assembly. The die is placed in a package in anupside flippedorientation in flip- chip, leaving a broad attack surface available for revealing the on-chipassetswithout any additional sample prepara- tion step. [1,7] Therefore, optical attacks can be considered as a “hurricane” moving toward the confidentiality and integrity of ICs. Advancedpackaging techniques can act as the first line of defense for IC assets against that hurricane. In recent years, researchers have proposed different prevention- and detection-based countermeasures to protect the chip backside from optical attack. The pre- vention-based approaches suggest adding opaque layers at the back of the die. Such a layer can easily be removed using polishing, or acid/plasma etching. [1-8] Conversely, a sensor-based approach can detect external photon stim- ulation, [9,10] at the cost of design resources, such as area and power overhead. This article explores different packaging techniques froma security perspective. The security threats imposed by state-of-the-art optical debugging techniques and the vulnerability of varying packaging are also surveyed in this study. A researchdirection todevelopapractical approach for security assurance against optical attacks is presented. PACKAGING TECHNIQUES To keep upwithMoore’s law, the outsourced semicon- ductor assembly and test (OSAT) companies and foundries have put an enormous amount of effort into developing the new advanced system in packaging (SIP), as shown in Fig. 1, including but not limited to fan-in, fan-out wafer- level packaging (WLP), [11] panel-level packaging, (PLP), and 2.5D and 3D packaging. Advanced IC packaging includes