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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 2 36 introduced the principle of operation, reviewed applica- tions, and shared case studies, specifically comparing carrier profiling methods. Depth sensitivity and applied bias became topics of discussion among the participants based on De Wolf’s talk. This evolved into a discussion on sample preparation with concerns regarding mounting and planarity being highlighted. The use of a diamond tip for material removal was suggested as a method for in-situ sample preparation. The session continued with Daksh Dharod from Intel introducing the topic: “Lock-in Thermography: Static and Dynamic Applications, 3DPackaging,”where he discussed the challenges for failure analysis on multi-stack dies. By implementing a tester-based solution in conjunctionwith the lock-in thermography camera receiving the stimulus of the tester, shorts in the substrate between the dies can nowbe isolated. NextNicholas AntoniouandRavi Chintala, fromPrimeNanoshared, “ScanningMicrowave Impedance Microscopy (SMIM) Case Studies.” After presenting the case studies, the participants debated the differences between SCM vs SMIM and analyzed the advantages of each technique. Prasoon Joshi fromIntel presented “Fault IsolationwithE-beamProbing (EBP).”Questions regarding the timing resolution limitations of using e-beam were answered. The conclusion was the use of a stroboscopic technique would overcome this barrier. As a framework for the next discussion, Doug Hunt from GlobalFoundries, presented, “The Other Side of the Spectrum: How We Identify Fails in Large Packages through Nano-probing and EBIC/EBAC.” New advanced packaging architectures are creating challenging require- ments for nanoprobing probe areas. The large packages now require up to a 70mmarea to be probed. A discussion on probe placement, and stage travel ensued. Next, Caleb Shin from Intel presented, “Fault Isolation on Functional Failures.” This was followed by a presentation by Kwame Amponsah from Xallent on, “Fine Pitch Probing of Thin Film Materials and Semiconductor Devices.” More than 140 people attended the virtual user group generating conversations full of robust intellectual content. Participants shared experiences and were open to enquiring on new technologies and applications. The session concluded with a review of the EDFAS FA Technology Roadmap. "NEW ADVANCED PACKAGING ARCHITECTURES ARE CREATING CHALLENGING REQUIREMENTS FOR NANOPROBING PROBE AREAS." SYSTEM ON PACKAGE VIRTUAL USER GROUP Moderators: Prasad Divekar and Kevin Distelhurst prasad.k.divekar@intel.com , kevin.distelhurst@globalfoundries.com The System on Package (SOP) User Group had its second successful discussion this year focused on the challenges posed by advanced SOP technologies to the failure analysis community. The group of panelists, Dr. Yan Li from Intel, Douglas Hunt from GlobalFoundries, Jesus “Dodie” Sampang from Intel, and Dr. Susan Li from Infineon in addition to the chairs navigated the issues and weighed solutions with feedback, thoughts, and ideas from the attendees. Dr. YanLi started thediscussionwithagoodoverviewof different SOP package types such as embeddedmulti-die interconnect bridge (EMIB) and chip-on-wafer substrate (CoWoS). She thenmoved to thepros/cons of using various FA tools and techniques on these package types. She went over fault isolation (TDR, LIT, MFI), nondestructive imaging (XRT, SAM), physical/destructive techniques (laser ablation, plasmaFIB, ion milling), and material analysis (EDX, SIMS) techniques. Attendees were interested in the different types of lasers used for high TPT mills and the solutions devised to accommodate large sample sizes in the various tools. A question was asked whether CNC pocket milling was used by anyone as a starting point for a large cross section. The panelists didmention some use of CNC to partially expose areas of these package types. The discussion moved to challenges when faced with interposer chip-to-chip internal IO (interconnect) fails on 2.5D packages. Douglas Hunt provided an excellent backdrop for this discussion providing case studies and experiences. Three different approaches were presented and the difficulties in each. He solicited suggestions from attendees on overcoming the interposer cracking when de-processing to and through the interposer silicon.