May_EDFA_Digital

edfas.org 35 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 2 SAMPLE PREP VIRTUAL USER GROUP Moderators: Jim Colvin and Bryan Tracy jim@fainstruments.com, btracy@tesla.com and pressures can be determined in real time for risk assessment duringprep. Thermalmanagement of thinned silicon was discussed as a cautionary tale both for crack risk in warped packages as well as second breakdown (thermal runaway). Colvin then concluded with some out of the box FA ideas for board level microsurgery and small package decapsulation. Bryan Tracy posed two topics as well. The first was a general focus on how to get to buried interfaces without destroying them so that imaging and microanalysis is possible with a minimum of artifacts. This was illustrated with two versions of a TEM sample preparation method which was able to access the copper wire to aluminum bond bad interface; a problem which has plagued the IC industry as a whole. The second topic was equally specific: how to access themolding compound to lead frame interface in the case of delaminationdetectedby CSAM. Thiswas fertile ground as many of the audience members had lived through the early and problematic introduction of epoxy molding compound (aka EMC). Audience participation was absolutely fantastic, and the session ran into overtime. We look forward to a similar session at ISTFA 2021 with increased focus on soliciting and answering audience member questions. The2021SamplePrepUser Groupwas a lively andwell- attended virtual sessionwithmore than 160 participants, lastingmore than two hours with questions, answers, and follow-ups going to ASM Connect for further and ongoing interaction. The User Group was moderated by Jim Colvin of FA Instruments and Bryan Tracy of Tesla who made short introductions to stimulate discussion. This triggered multiple questions from the audience. Colvin gave an overview of ultra-thin silicon sample prep challenges on2.5D/3Dpackages anddiscussed issues with different die heights with adjacent die on 2.5D. The challengesonCoWoSandDDR4 stackeddiepackageswere discussedwith an example of die removal down to die 8 in a DDR4 assembly. Challenges with package warpage and ultra-thin siliconwere shownwithmesh overlaymodels to correct siliconnon-uniformities. Less than100nmvariance was demonstrated over a 2 mm x 2 mm pocket. Colvin’s second presentation was titled “Rework Avoidance – Board-Level Die Thinning and Thermal Management.” Thinning the attached device on the motherboard avoids risk of failure due to rework and/or recovery of the failure. Restricting the liquid coolant to the die surface with accompanying suction and/or with a temporary cavity for the coolant allows the board to be operated while thinning and/or polishing. Removal rates CONTACTLESS PROBING AND NANOPROBING VIRTUAL USER GROUP Moderators: Dan Bockleman, Daminda Dahanayaka, Neel Leslie, and Sara Ostrowski dan.bockelman@intel.com, daminda.dahanayaka@globalfoundries.com , neel.leslie@thermofisher.com, saraostrowski@eurofinseag.com This year theContactless andNanoprobingEDFASUser Group transitioned to a virtual platform. The new virtual platform provided for an open forum where attendees could share and discover new technologies. The session featuredseven focusedpresentations to initiateandstimu- late insights, leading to anopendiscussion among the par- ticipants. These focused topics covered a comprehensive range of failure analysis techniques including, scanning probe microscopy (SPM), lock-in thermography (LIT), e-beamprobing, optical fault isolation, and nanoprobing. The first presentation was conducted by Peter De Wolf from Bruker. His presentation was titled “Scanning Capacitance Microscopy and Scanning Spreading ResistanceMicroscopy for Nanoscale Carrier Profiling.” He