May_EDFA_Digital

edfas.org 1 1 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 2 FUTURE WORK As shown in this article, for advanced 2D and 2.5D packaging, where dies are horizontally placed, the optical attack appears to be a threat to the chip’s confidentiality, availability, and integrity. For the new advanced packag- ing, the existing counter measurements for the optical attack need to be re-evaluated. Not only to find whether they are still effective for the new packages but also to discuss the compatibility. What’s more, the complexity of advanced packaging brings more opportunities for countermeasures. Passive and active components can be added into the advanced packaging to block, scatter, or detect the input laser. For instance, an embedded optical sensor in the packaging can be used to monitor all kinds of optical attacks. From the IC design level, hiding the POI might be a possible approach for the advanced packaging with multiple functionalities die. Increasing the difficulty of localizing the POI will also increase the attack cost without affecting the failure analysis. For the 3D packaging, which vertically places the dies, the optical attack will be different. The upper layer is as vulnerable as the other types of IC packaging. Countermeasures should also be employed to protect the die from optical attacks. However, whether the optical attack can be placed remains unknown for the under- layer dies. Because the optical attack requires a fully functional chip and the removal of the top layer of the 3D packaged chips, it will destroy the electrical intercon- nection. The security assets store in the lower layer of the chip seems to be well protected. However, this might be solved by sample preparation technology development. The vulnerabilities of the under-layer dies also should be assessed. Nowadays, 3D packaging is only used in limited applications, most of them are high bandwidth memory. However, themoving trend is inevitable. Secured advanced packaging is needed to protect dies frombeing assessed or modified by adversaries. Along with the prevention-based approach, it is also necessary to develop a preventive approach against optical attacks to address the vulnerabilities of advanced packaging. Therefore, it is necessary to develop a suit- able metric to define the vulnerabilities of the packaging against a different class of physical attacks such as optical attacks and electrical probing. In addition to developing suitable masking techniques to hide the circuit activity and developing polishing detectors at the backside of the chip, suitable sensors to identify the package removal can significantly increase the time, and cost of the above- mentioned attacks, hence improving the security of the advanced packaged ICs. CONCLUSION This paper introduces the development trend of IC packaging and, to bemore specific, the packaging’s inter- connection technology development. It turns out that the flip-chip technology will be applied in the majority of advanced packaging to meet high bandwidth require- ments. Then a comprehensive study of optical attacks is presented, including different types of optical attacks and the steps to place these attacks. It appears that optical attack is a dire threat to existing security assets, and this threat will become more severe for advanced packaging with flip-chip interconnections. Based on the adversaries’ capabilities and security assets availabilities, different kinds of threatmodels have beendeveloped. These classi- fied threatmodels canbe used for the security assessment of the advanced IC packaging and can help evaluate the efficiency of the newcountermeasure approaches. Finally, the article shows state-of-the-art countermeasures, and with the help of the newly developed threat models, the limitation of these schemes has been presented. Though 100% eliminating the effect of optical attack remains unachievable, understanding the attack approach and potential adversaries helps to know the perniciousness of it and urges the community to develop new security schemes for protecting the chip backside fromunauthor- ized access. REFERENCES 1. M.T. Rahman, et al.: “Physical Inspection & Attacks: New Frontier in Hardware Security,” 2018 IEEE 3rd International Verification and Security Workshop (IVSW), IEEE, 2018, p. 93–102. 2. A. Schlosser, et al.: “Simple Photonic Emission Analysis of AES,” International Workshop on Cryptographic Hardware and Embedded Systems, Springer, 2012, p. 41–57. 3. S. Tajik, et al.: “Laser Fault Attack on Physically Unclonable Functions,” 2015 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), IEEE, 2015, p. 85–96. 4. S.P. Skorobogatov and R.J. Anderson: “Optical Fault Induction Attacks,” International Workshop on Cryptographic Hardware and Embedded Systems, Springer, 2002, p. 2–12. 5. H. Lohrke, et al.: “Key Extraction using Thermal Laser Stimulation,” IACR Transactions on Cryptographic Hardware and Embedded Systems, 2018, p. 573–595. 6. S. Tajik, et al.: “On the Power of Optical Contactless Probing: Attacking Bitstream Encryption of FPGAs,” Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, ACM, 2017, p. 1661–1674. 7. M.T. Rahman, et al.: “Defense-in-depth: A Recipe for Logic Locking to Prevail,” arXiv preprint arXiv:1907.08863 , 2019. 8. M. Rahman and M. Dewan: “Analytical Determination of Collisional SheathProperties for TripleFrequencyCapacitivelyCoupledPlasma,” IEEE Transactions on Plasma Science, 42, (3), 2014, p. 729–734. 9. S. Tajik, et al.: “Pufmon: Security Monitoring of FPGAs using Physically Unclonable Functions,” 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), IEEE, 2017, p. 186–191.