51ST INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS NOVEMBER 16–20 | PASADENA CONVENTION CENTER, PASADENA, CA For dates, times, and full course descriptions, visit istfa.org. Join the microelectronics failure analysis community by attending our premier event, the 51st International Symposium for Testing and Failure Analysis, November 16-20 in beautiful Pasadena. The theme—Scaling Beyond Moore’s Law: Heterogeneous Computing and Advanced Packaging—will serve as a focal point in user group meetings, technical presentations, and keynotes. The conference also includes the highly popular EDFAS video and photo contests. EDUCATION WORKSHOPS • Beam-based Defect Localization Instructor: Dr. Ed Cole, Jr., FASM • Physical Failure Analyses for Solving Problems Instructor: Wentao Qin Organized By: ISTFA once again o ers the opportunity to take an immersive half- or full-day educational course. This year’s tutorial program extends the learning process to a wider selection of topics. The technical sessions feature over 100 presentations of original unpublished work in areas such as sample preparation and device deprocessing, AI applications for FA, scanning probe analysis, emerging FA techniques and concepts, as well as a CHIPS Act update. In addition, the popular Expo features key companies showcasing the best technologies and products in the industry. Sponsored By: TUTORIALS An expanded tutorial program addresses 26 topics, including several new ones. WEDNESDAY, NOVEMBER 19 The speaker information and abstract for Wednesday’s keynote session will be announced on the event website at istfa.org. TUESDAY, NOVEMBER 18 Dr. Raja Swaminathan, Corporate Vice President of Heterogeneous Integration Technologies at AMD, will talk on “Future of AI Hardware Enabled by Advanced Packaging.” New heterogeneous architectures like 2.5D architectures and 3D hybrid bonded architectures driving AMD’s industry-leading, advanced technology roadmap to enable power, performance, area, and cost (PPAC) will be discussed. The talk will also address chiplets for AI, as well as challenges and solutions for large chiplet modules. KEYNOTE SESSIONS
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