NOVEMBER 16–20, 2025 PASADENA CONVENTION CENTER | PASADENA, CA SCALING BEYOND MOORE’S LAW: HETEROGENEOUS COMPUTING AND ADVANCED PACKAGING SAVE THE DATE! High-performance compute solutions are simultaneously driving innovations in advanced packaging, high bandwidth I/O, heterogeneous compute architectures, device architectures, silicon scaling, and more. Each of these advances pose a unique challenge to failure analysis, but together present a disruption that the failure analysis community has yet to experience. Now is the time to act! New analysis methods and instrumentation must be developed to address these challenges and deliver the stellar analysis capability our failure analysis community is known for. Industry collaboration is the key to success. Together, we will spearhead the breakthrough approaches necessary to overcome the complex disruptions our society is facing as high-performance compute solutions scale beyond Moore’s law. STUDENT POSTER SESSION The 51st International Symposium for Testing and Failure Analysis (ISTFA) invites community college, undergraduate, and graduate students to participate in this year’s student poster contest. This program is designed to: • Foster exchanges between academia and the failure analysis engineering community. • Provide students with an opportunity to gain exposure to failure analysis within the microelectronics sector and to network with professionals and peers in the field. ISTFA is the premier microelectronics/semiconductor failure analysis conference in North America. It will be held at the Pasadena Convention Center from November 16–20, 2025. Learn more at ISTFAevent.org. •Access to tutorials •Four days of technical programming •Keynotes & Panel Discussion •Entrance to the Exhibit Hall Complete Full Conference Ticket Includes: Student Registration Available •Welcome Reception with the Exhibitors •Refreshment Breaks each day •Lunch vouchers •One ticket to the Social Event REGISTRATION OPENS IN JULY!
RkJQdWJsaXNoZXIy MTYyMzk3NQ==