edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 3 54 GUEST COLUMNIST of bulk silicon without affecting device functionality. Plasma FIB (PFIB) planar delayering has become popular at the advanced nodes due to aggressive scaling of interconnect layers. Delayering of thick upper metal Cu layers and areas with varying metal line density suffers from non-uniform delayering. Airgap ultra-low-k delayering at lower metal lines could also present challenges. PFIB ion-beam and e-beam impact on transistors is not well documented and additional work will be needed to better understand the beam-device interactions. Advanced automation of PFIB delayering, including end-pointing, will be needed for increased throughput while maintaining the success rate. Transmission electron microscopy (TEM) lamella sample preparation gets harder as the feature and defect sizes are in sub-nanometer range. Ultra-thin lamella below 30 nm thickness with minimal amorphization and Ga implantation are required. For preparing site specific lamella, end pointing at the region of interest with defect embedded within sample presents another gap. Nanoprobing, an essential defect localization and device characterization step, involves conductive probes physically contacting individual device structures. This process faces ongoing challenges due to device scaling and new process architectures. Smaller nodes with tighter geometry make it more difficult for probe tips to land on specific transistor terminals, particularly when multiple probe tips must be landed on tiny structures simultaneously. Sharper and more durable probe tips with optimized geometry are needed, along with continuous improvements in imaging resolution, lower landing energy, reduced surface carbon deposition, and sample drift. Localization of defects in three-dimensional structures, like GAA and BPR architectures, presents new Rapid advancements in logic and memory scaling have been driven by the introduction of new materials, such as cobalt (Co) and ruthenium (Ru), and innovative transistor architectures like gate-all-around (GAA) devices and upcoming buried power rail (BPR) devices. These developments present numerous challenges, which are further compounded by the integration of advanced heterogeneous packaging technologies such as chiplets, 2.5D, and 3D devices. To address these challenges, the Die-Level Post-Isolation Domain Council was established, which aims to consolidate the challenges and develop a roadmap for tackling them in a comprehensive and strategic manner. Die-level failure analysis typically consists of two major sequential steps. The first step, fault isolation, involves using software diagnostics, ATE testers, and various optical-based fault isolation techniques to narrow down the faulty area. The second step, post-isolation, focuses on further localizing the defective structure and conducting detailed electrical, physical, and material characterization to identify the defect, understand failure mechanisms and establish root cause of failure. Due to the complex nature of die-level failure analysis, multiple analytical techniques have proven to be indispensable for successful root cause analysis. These techniques primarily fall into five categories: sample preparation, microscopy, nanoprobing, circuit editing, and scanning probe microscopy. Sample preparation is crucial for successful failure analysis, as it enables each of the analytical techniques throughout the fault isolation, defect localization, and physical analysis stages. Complex packaging integration schemes make it difficult to prepare the target die for analysis without damaging the other components. Higher-resolution optical fault isolation and electron beam probing techniques are driving the need for ever thinner remaining silicon thickness or even complete removal THE EDFAS FA TECHNOLOGY ROADMAP DIE-LEVEL POST-ISOLATION DOMAIN TECHNICAL SUMMARY Chuan Zhang, Nvidia chuanz@nvidia.com Zhang
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