edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 54 GUEST COLUMNIST application developments are feasible and highly desirable in the fields including: 1) Assisting FA data collection on different tools or performing full FA; 2) Training new FA engineers on FI-FA tools; 3) Generationormodification of detailed measurement data from rare failure modes of different samples; and 4) Automatic FA report generation and evaluation. The availability of hundreds or thousands of standardized training datasets for each failuremode is the key to successful AI execution in FA. The restrictions of AI application in FA are in the fields where only small training datasets are available. How to normalize and share training data for generic failure modes in semiconductor devices, and how to develop AI algorithms without hundreds or thousands of training datasets are very imperative and challenging topics. Heterogeneous integration typically results in much larger packages, due to the assembly of multiple chiplets and stacked dice with various functionalities. Optical or infrared microscopes, SAM, 2D or 3D x-ray tools, and fault isolation techniques, which can accommodate large sample size are highly desired. Furthermore, die stacks and chiplet architecture in advanced packages requires better Z dimensional resolution in fault isolation. Additionally, smaller and denser die-to-die interconnects do not have direct connections for electrical testing, thus demand superior resolution for nondestructive imaging approaches, and precise sample preparationmethodologies to reveal tiny defects in complicatedpackages. Recent SAM and 3D x-ray technical developments in large field of view (FOV) imaging with improved resolution and shorter TPT, as well as various advanced sample preparation techniques are reviewed. Fast and successful FA relies on high performance and robustness of analysis tools. A list of desired tool reliability and durability improvements is identified, which could The semiconductor industry is now relying on breakthrough innovation and investment in advanced packaging as silicon technology scaling encounters barriers moving forward. 3D or advanced microelectronic packaging is the industry trend to meet the ever-increasing market demand for increased performance, reduced power consumption, smaller footprint, lower cost, and integration of heterogeneous devices. Innovations in package failure analysis are critical to the success of advanced packaging technology development by providing timely feedback and solution paths to device yield issues or reliability test failures. The high level of functional integration and the complex package architecture in advanced 3D packages pose a significant challenge for conventional fault isolation (FI) and failure analysis (FA) methods. In addition, high-volumemanufacturing requires an innovative FA flowwhich is cost-saving, feasible of supporting high volume products, and with short through-put time (TPT). The Package Innovation Roadmap Council (PIRC) technical paper highlights recent innovations, technology gaps, and future development trends in package FI and FA, including three main categories: 1) Artificial intelligence (AI) applications, 2) Sample handling, and 3) FA tool robustness. Integrating AI into FA flow promotes automation and big data analysis, which saves human resources and costs, shortens TPT, and enables high volume FA support on very complicated microelectronic devices. Prospective progresses have been made in the following areas: 1) Defect detection and classification; 2) Noise reduction in scanning electron microscopy (SEM), transmission electronmicroscopy (TEM), scanning acoustic microscopy (SAM) and x-ray images; 3) Failure mode identifica-tion by clustering and pattern recog- nition; and 4) Failure analysis data and report classification, as well as failure mode prediction. Future AI PACKAGE INNOVATION ROADMAP COUNCIL (PIRC) TECHNICAL SUMMARY Yan Li, Intel Corp. yan.a.li@intel.com Li
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