edfas.org 35 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 for FA to successfully isolate elusive defects as “More Moore” and “More than Moore” make analysis evenmore challenging. He pointedout the importance of “goingback tobasics” inFAworkflow: automated test equipment, nondestructive imaging, electrical fault isolation, and finally precise sample preparation and imaging. He described the challenges of each step and the limitations of several FA tools. Li followed up the discussion by summarizing the challenges of isolating elusive defects into two broad categories: technical challenges (e.g., advanced technology node and packaging, and metrology limitations) and logistic challenges (e.g., limited manpower, budget, and lack of design support). She proposed solutions to overcome these challenges, and these included integrating design/testing/FA techniques, utilizing AI/ML for history search, and developing new tools and techniques. hinskywas askedwhether therewas a need to design new ESD protection circuitries for new technology processes such as gate-all-around field-effect transistor (GAAFET), to which he answered that fundamentally, the ESD protection approach does not change, but specific devices used to build protection may be different. There are currently still challenges to reduce the ESD standards stress levels further, including the issues with the ESD tester itself. The application of AI/ML in FA to isolate elusive defects in amassive FA request (e.g., yield improvement) garnered considerable interest. To incorporate AI successfully, FA labs need to acquire a large amount of data. Getting fab defect data (ADR/ADC) would be a jumpstart for any FA lab’s intelligence system, at least in the area of visual defects. After localizing defects, it would be helpful to tap the fab data to better understand failuremechanisms and fix yield issues. Incorporating AI for datamining of fab data could help to identify defects in a shorter cycle time. AI could also be used to classify defects in the database, enabling engineers to quickly search for previously logged defects. When comparing emission or passive voltage contrast results fromfailed and reference devices, AI could theoretically help identify the abnormal sites instantly and accurately insteadof engineersmanually identifyingwhich ones were abnormal in a tedious approach. Because FA is now becoming more complicated and time consuming, the consensus was that it has become impossible toperformthe same amount and level of work. FA labs have limited resources and are unable to support all yield issues. To overcome this, it was suggested to use wafer level scan diagnosis to find common scan chain failures aswell as the applicationof AI and statisticalmethods to increase the FA success rate. A discussion onwhether it was possible tonarrowdown toa single latch through scan chain diagnosis was also brought up. It was also noted that design for FA should be involved in the early stages. The dynamic Panel Discussion proposed several new and interesting ideas, highlighting the importance of the FA Roadmap council and propelling the need for close col- laborationbetweenvendorsandcompanies.Overall, itwas an engaging, fruitful, and stimulating session with pan- elists and attendees actively exchanging information. “INCORPORATING AI FOR DATA MINING OF FAB DATA COULD HELP TO IDENTIFY DEFECTS IN A SHORTER CYCLE TIME.” “...RESOLUTION LIMITATION OF FAULT ISOLATION TECHNIQUES WAS THE BIGGEST ROADBLOCK IN OUR ABILITY TO ISOLATE ELUSIVE DEFECTS...” Continuing Li’s reference to new tools/techniques, Ravikumar shared his extensive experience in fault isolation. He first discussed the resolution limitations of photon emission and visible light probing before putting forward the technique of e-beam probing, which is potentially an attractive technique because of the resolution it can achieve. However, the technique is extremely difficult and fault isolation might render itself useless with the arrival of buried power rail and “More Moore,” triggering the discussion on the importance of diagnostic capability, test and pattern customization, and design for FA. As though these problemswere not enough for FA engineers, Khazhinsky presented some of the ESD and latch-up challenges in designing advanced technology devices in advanced 3D packaging. For example, additional ESD protection is needed, resistive routingmust be taken care of, and the ability to individually test each die inmulti-die devices must be available in advanced 3D packaging. The trend in industry is also to reduce the ESD passing voltage requirement in HBM/CDM to meet demanding IC performance requirements in smaller devices with advanced technology nodes, leading to even more challenging FA. The unique perspectives were followed by an active open discussion between panelists and attendees. Khaz-
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