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edfas.org 33 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 23 NO. 1 that the future edge processing CNN system can also handle this 30 FPS load requirement to be suited for a real-time application module. The ultra-compact device size of the RRAM and the possibility to fabricate densely packed RRAMmemory enable duplicated trainedweights to be used by the symmetric computation pipeline for processing frames in parallel. By computing image frames in parallel, we may be able to further reduce the require- ments on the clock speed as well as the overall power consumption for on-the-fly decisionmaking edge devices for IoT, surveillance security, autonomous vehicles (self- driving cars) and many other niche applications . ACKNOWLEDGMENT N.L. Prabhu would like to thank the Ministry of Edu- cation, Singapore for providing the doctoral research student scholarship at SUTD for 2018-2021. N. Raghavan would like to acknowledge the financial and logistical support from the A*STAR BRENAIC Research Project No. A18A5b0056, which enabled thework tobe accomplished. REFERENCES 1. W. Zhang: “Shift-Invariant Pattern Recognition Neural Network and its Optical Architecture,” Proc. Annu. Conf. Jpn. Soc. Appl. Phys., 1988. 2. W. Zhang, et al.: “Parallel Distributed Processing Model with Local Space-Invariant Interconnections and its Optical Architecture,” Appl. Opt., 1990, 29.32, p. 4790-4797. 3. A. Kyriakos, et al.: “High Performance Accelerator for CNN Applications,” Intl. Symp. Power Timing Mod., Opt. Sim. (PATMOS), IEEE, 2019. 4. S. Yu: “Resistive RandomAccessMemory (RRAM),” Synthesis Lectures on Emerging Engineering Technologies 2.5 , 2016, p. 1-79. 5. F. Zahoor, T.Z. Azni Zulkifli, and F.A. Khanday: “Resistive Random Access Memory (RRAM): An Overview of Materials, Switching Mechanism, Performance, Multilevel Cell (MLC) Storage, Modeling, and Applications,” Nanoscale Res. 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ABOUT THE AUTHORS Lakshmana Prabhu Nagaraj has over 18 years of experience in industrial product design and development, specializing in machine vision and cloud computation. He previously served as the director of ALAI Technology Labs India Pvt. Ltd. He is currently pursuing his Ph.D. examining the impact of RRAMdevice level variability as an in-memory computational circuit for deep learning neural network (DNN) applications. He has four scientific publications to his credit relating to construction methodology for look-up table modeled RRAM based synaptic weight simulation framework and quantification of the DNN prediction error rate for given RRAM device level variability. NagarajanRaghavan is an assistant professor at the Singapore University of Technology and Design (SUTD) in the engineering product development pillar. Prior to this, he was a postdoctoral fellow at the Massachusetts Institute of Technology (MIT) in Cambridge and at IMEC in Belgium, in joint association with the Katholieke Universiteit Leuven. He obtained his Ph.D. (micro- electronics, 2012) at thedivisionofmicroelectronics, NanyangTechnological University, Singapore. His work focuses on design for reliability, physics of failuremodeling of nanodevices, as well as reliability assessment of edge computing hardware using non-volatile memory devices. He is the recipient of the IEEE Electron Device Society (EDS) Early Career Award for 2016, Asia-Pacific recipient for the IEEE EDS PhD Student Fellowship in 2011 and the IEEE Reliability Society Graduate Scholarship Award in 2008. To date, he has authored or co-authored more than 200 international peer-reviewed publications and five invited book chapters as well. He serves as the general chair for IEEE IPFA 2021 at Singapore and is also the associate editor of the IEEE Access journal.