February_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 23 NO. 1 32 and HRS resistance data sets, respectively. Five trials of simulation are performed for each convolution schema and compliance setting and the average error values are plotted here. We see that the prediction error for a simple single stage 1 × 1 convolution increases from just 5% to almost 50% as we reduce the value of I comp from 10 μA to 2 μA (not even an order of magnitude reduction in compliance), while the power consumed reduces by almost an order of magnitude (as represented in Fig. 4b). With increasing overlap in the HRS and LRS distributions at lower I comp , a lot more bits get falsely encoded in the hardware simulation flowresulting in themagnified image classification error here. Four different inception channels are employed to analyze the dependence of network complexity on the trend in prediction error rate accounting for compliance sensitive device variability. The first channel is a single layer (1×1 convolution) followed by incremental addi- tion of one layer at a time to the next channels, as in Figures 4a and b. As expected, for an increase in network size, the number of synaptic weights is higher, which also results in a higher prediction error rate in the hardware flow, as evident in Fig. 4a. When the classification is re-run with the same current compliance, we observe that the prediction error variation can be around 20%. This varia- tion is inherent because the RRAM resistance values are simulated and encoded as synaptic weights. Moreover, it is worth noting that if the false logic-0 or false logic-1 encoding happens at amore significant bit in themantissa of the floating point represen- tation of the synaptic weight, the prediction errors will be obviously more aggravated. INFERENCES AND CONCLUSIONS The simulated results quantify the increase in power consumption when the RRAM device is used at a higher compliance, which caters to a wider memory window and lower overlap in the LRS and HRS state resistance distribu- tions. Clearly, there is a trade- off involved in the power consumption and the desired accuracy of the hardware neural network (as variability in RRAM resistance is inevita- ble) and the sweet spot for operating the edge computing hardware will very much depend on the end use applica- tion requirements and constraints. To further improve the accuracy-power tradeoff inhardwareneural networks, it is necessary toexplorealternativematerial stacks anddevice architecture of the RRAM (say by exploring multi-layer dielectrics instead of a single one) so as to achieve better control of the oxygen vacancy or metallic filamentation process that in turn governs the resistance variability of these devices in the two binary states. The salient objective of building an RRAM synapse for today’s CNN is to construct truly edge compatible self- thinking cameras, employed in remote areas and appli- cations. RRAM’s multi-bit property (analog conductance tunability) is a very appealing feature, making it the right choice for neuromorphic applications. The CNN trained weights are stored in a 32-bit floating-point (FP32) format in any given digital memory as mantissa, exponent, and sign bits, respectively. Thus, the multi-bit property will be a promising feature to encode the 32-bits of trained weights to a lower order bit size, depending on the resolu- tion and control over the multi-level switchability of the RRAM. Additionally, the workaround to handle the device level variability is by encoding the multi-bit valued RRAM on the 24-bit mantissa part of the FP32 bits and avoid the exponent and sign bits so as to reduce the prediction error rate in RRAM synapses. At a higher level, today’s vision systems nominally cap- ture 30 frames of images per second (FPS). It is essential Fig. 4 (a) Classification error rate plotted for varying RRAM current compliance (2 µA, 5 µA, and 10 µA) for different cascaded convolution schemes ranging all the way from 1 × 1 to 1 × 1 → 3 × 3 → 3 × 3 → 3 × 3 . Withmore cascaded layers of convolution, the prediction error rate increases significantly in a hardware network due to compounded effects of incorrect weight computations due to variability induced false binary bit encoding, which is more serious for very low compliance switching (ultralow power regime of RRAM); (b) Power consumption per bit for the different cascaded convolution layers for current compliance of 2 µA, 5 µA, and 10 µA. (b) (a)