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edfas.org 29 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 23 NO. 1 COMPUTATIONAL FAILURE ANALYSIS OF RESISTIVE RAM USED AS A SYNAPSE IN A CONVOLUTION NEURAL NETWORK FOR IMAGE CLASSIFICATION Nagaraj Lakshmana Prabhu and Nagarajan Raghavan Singapore University of Technology and Design, Singapore nagarajan@sutd.edu.sg EDFAAO (2021) 1:29-33 1537-0755/$19.00 ©ASM International ® INTRODUCTION Today, the vision processing era’s rise is substantiated by the ubiquitous nature of image-based applications in day-to-day life, from the simple household surveil- lance system to complex industrial process automation. The advancement of CMOS technology has significantly contributed to the rapid progress in the visual sensor industry. This engenders deep learning or convolution neural network (CNN) to be the de facto standard for visual analysis on the edge. CNN is constructed on a shift-invariant neural network based on shared-weights architecture for pattern identification in a parallel and pipelined structure for fast and real-time applications. [1,2] The computational performance of CNN is intense and hence significant amount of investigation and archi- tectural evolution of the network (with different series- parallel arrangement of the convolution blocks) for accuracy improvement has been carried out using the basic structure and computational scheme around this algorithm. The CNN structure is being configured to be deeper and wider to improve the classification (predic- tion) accuracy, resulting in higher computational load (operation) per bit. This improved algorithm/software- based classification performance on the cloud, however, limits CNN’s ability to be truly edge compatible with the high operational power and low latency required for on- the-fly efficient computation and quick decision making for critical systems such as self-driving cars and delivery drones. [3] The in-memory computation is significant over the traditional Von Neumann architecture scheme as it reduces the undesirable energy wall resulting from con- stant data exchange between thememory and processing unit for every command execution. RESISTIVE SWITCHING MEMORY FOR HARDWARE AI Resistive random access memory (RRAM) is undoubt- edly a popular candidate for in-memory computing architecture designwith ultralowswitching power, simple process scheme, analog conductance tunability and Fig. 1 (a) Various NVM technologies being explored for neuromorphic systemrealization (resistive RAM, [7] phase change RAM, [8] ferroelectric RAM, [9] spin transfer torque RAM, [10] NAND flash, [11] carbon nanotube [12] ); (b) Comparison of the standard performance and reliability metrics for the currently popular NVM technologies. (b) (a)