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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 23 NO. 1 18 REFERENCES 1. K.R.Williams,K.Gupta,andM.Wasilik:“EtchRatesforMicromachining Processing-Part II,” J. Microelectromech. Syst., 12 (6), Dec. 2003, p. 761- 778, doi: 10.1109/JMEMS.2003.820936. 2. S.D. Bennett, et al.: “Integrated Circuit Metrology with Confocal Optical Microscopy,” Philos. Trans. R. Soc., A, 320 (1554), 2020/09/24 1986, p. 307-313, doi: 10.1098/rsta.1986.0119. 3. K. Mahmood, P.L. Carmona, S. Shahbazmohamadi, F. Pla, and B. Javidi: “Real-time Automated Counterfeit Integrated Circuit Detection using X-ray Microscopy,” Appl. Opt., 54 (13), 2015, p. D25- D32, doi: 10.1364/AO.54.000D25. 4. S.A.C. Gould, et al.: “From Atoms to Integrated Circuit Chips, Blood Cells, and Bacteria with the Atomic Force Microscope,” J. Vac. Sci. Technol. A, 8 (1), 2020/09/24 1990, p. 369-373, doi: 10.1116/1.576398. 5. A. Kimura, et al.: “A Decomposition Workflow for Integrated Circuit Verification and Validation,” J. Hardw Sys. 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Goodfellow, et al.: “GenerativeAdversarial Nets,” Proc.ICONIP , 2014. 12. A. Waite, J. Scholl, J. Baur, A. Kimura, M. Strizich, and G. D. Via: “IC DecompositionandImagingMetricstoOptimizeDesignFileRecovery for Verification and Validation,” GOMAC Tech , San Diego, CA, 2020. 13. A. Kimura, A. Waite, J. Scholl, J. Schaffranek, M. Sutter, and G.D. Via: “From Silicon to Simulation: A Full Decomposition of a Fabricated 130 nm Serial Peripheral Interface for Establishing an Assurance Baseline Root-of-Trust,” IEEE PAINE, 2020. 14. A. Kimura: “Development of Trust Metrics for Quantifying Design Integrity and Error Implementation Cost,” Electronic Thesis or Dissertation, Ohio State University, 2017, Available: http://rave. ohiolink.edu/etdc/view?acc_num=osu1492607691591962. for assessing functional verification decompile the recov- ered netlist and represent it as a graph. This allows for a muchdeeper analysis of thenetlist andprovides a scalable method for doing a full equivalence evaluation of the as- fabricated netlist to the golden reference. CONCLUSION There is no single “silver bullet” approach to assuring microelectronics, thus a litany of verification and valida- tion techniques are required to obtain thorough verifica- tion coverage. Each technique has limitations that may not provide enough observability to capture a malicious modification or feature. As such, the aggregation of all the physical and functional verification techniques can provide a much more thorough and robust assessment. Theprerequisite toapplyinganyof theseassuranceassess- ments, however, begins with the accurate recovery of the IC’s design files. To this end, one could argue that sample preparation and image acquisition are the most critical stages of the entire assurance process flow. Errors and mistakes made in these early stages propagate through the decomposition stages and create errors in the netlist or GDSII layout. As themicroelectronics industry continues to forge onward to sub 5 nmdesigns composed of billions of devices, the pressure remains on the materials science andmicroscopy communities to continue to innovate and advance the state-of-the-art of failure analysis tools. This is the only way the trust and assurance community will be able to assess and assure advanced microelectronics. ACKNOWLEDGMENT Distribution A: Approved for Public Release, Approval ID: 88ABW-2020-3202. TOOLS AND TECHNIQUES TOWARD INTEGRATED CIRCUIT TRUST AND ASSURANCE (continued from page 16) ABOUT THE AUTHORS Adam Kimura is a senior cyber scientist at Battelle Memorial Institute and has been working in the field of trusted and assured microelectronics since 2013. His research experience spans the verification and validation of integrated circuits, integrated circuit decomposition, and developing novel techniques for quantifying hardware assurance in advanced node devices. He currently holds his B.S, M.S., and Ph.D. in electrical and computer engineering from The Ohio State University. Jonathan Scholl is a lead materials engineer at Battelle Memorial Institute where he works on sample preparation of integrated circuits. He has a B.S from The Ohio State University in materials science and engineering specializing in electronicmaterials and a M.S fromThe Ohio State University in biomedical engineering specializing inmicro/nano devices. His research interests are in delayering advanced integrated circuits for design validation and automating sample preparation tools.