February_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 23 NO. 1 16 Three primary imaging challenges arise as these tech- niques are applied to advanced node ICs: 1) approaching the resolution limit of the imaging tool, 2) the exponential increase in acquisition time for the region of interest, and 3) the extraordinary data storage and processing requirements for the massive amount of imagery col- lected. Device scaling leads to decreased feature sizes as well as increased design complexity which will exact a heavy price on the imaging process and analysis. In order to meet the required resolution for feature extraction and polygon vectorization, extraction algorithms have minimum resolution limits where a feature can no longer be identified or distinguished from its neighbor. [12] For advanced technology nodes, features can approach the single digit nanometer range, requiring image resolutions of a nanometer per pixel or less, which is at the limit of the highest resolutionSEMavailable. As higher resolutions are required to image advance technology nodes, thiswill lead to an increase in acquisition time. Image acquisition scan times will grow exponentially from a few hours to several weeks for a single layer. As the image acquisition time is increased, this will begin to generate a massive amount of high-resolution imagery which will not only have to be stored, but processed, requiring a significant investment in computational hardware. Todemonstrate the scaling issueand its three challeng- es tobeaddressed, consider two ICs, both1mm 2 in sizebut at 130 nmand 14 nm technology nodes, respectively. The smallest feature layer in the 130 nm node IC will require around 25 nm per pixel resolution, while the smallest feature layer in the 14 nm node device layer will require 1 nmper pixel. Assuming anominal 2µs dwell timeper pixel, the 130 nmnode IC layer will take about 8 hours to acquire in a SEM. The 14 nmnode layer will require an acquisition time of a little over 29 days. Furthermore, assuming the image files are industry standard 8-bit lossless TIFF files, every pixel will equal one byte of data. The 130 nm node devicewill require 4.9 GB of imagery for that layer of inter- est, while the 14 nm node IC will require 1.25 TB. PHYSICAL AND FUNCTIONAL VERIFICATION AND VALIDATION OF RECOVERED DESIGN FILES After the features of the IC have been extracted and converted to polygons across every layer of the chip, the as-fabricated GDSII layout can be generated and com- pared back to the original golden layout. Figure 5 shows the recovered as-fabricated layout (left) along with the original golden reference layout (middle). When a differ- ence operation is performed between the two layouts, the result (right) illuminates fill features that were added at the foundry that were not in the original design. [13] This provides an easy way of quickly identifying unknown fea- tures or modified areas of the layout that require deeper analysis. The physical verification through feature matching between the two layouts is one component of assuring a chip, however, additional assessments need to be com- pleted for verifying the functional design of the recovered layout. To this end, a netlist can be generated from the design layout. The netlist contains the full connectivity of all the standard cells or devices in the layout. With an as-fabricated version of the netlist, logical equivalence checks can be conducted against a reference golden netlist as well as model checking simulations run in the original verification testbenches. [14] Althoughbothof these verification techniques are good formediumsize designs, formalmethods tend tonot scalewell as designs get larger. Functional model checking also suffers in coverage as designs scale up in size and complexity. New techniques (continued on page 18) Fig. 5 Detail region of the SPI module showing the recovered as-fabricated GDSII, left, the golden design GDSII, middle, and difference between both, right.