February_EDFA_Digital

edfas.org 15 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 23 NO. 1 sample preparation more of an art rather than a science. In addition to this, increasing design complexity, shrinking process nodes in new materials, and advanced packag- ing in microelectronics are now exceeding the limits of the current state-of-the-art tools and techniques, thus creating a demand for innovation and advancement. As such, a new generation of sample preparation tools are being developed to better address the requirements for advanced IC sample preparation. FULL-LAYER IMAGE ACQUISITION The sample preparation stage processes the IC until the target layer is sufficiently exposed for imaging. The image acquisition stage works in tandem with sample preparation. As captured in Fig. 3, after a target layer is exposed, it is sent for imaging and then brought back to the sample preparation stage for continued delayering down to the next target layer. The imaging of each layer captured between delayering processes outputs a ser- pentine arrangement of image tiles that are stitched into a mosaic representative of the entire layer. This process is repeated iteratively until all metal, via, polysilicon, and implant region layers have been captured. There are a handful of imaging techniques that can be applied to a serial decomposition of an IC including optical microscopy, [2] x-ray microscopy, [3] scanning probe techniques (atomic forcemicroscopy, etc.), [4] and scanning electron microscopy. [5] Optical microscopy offers incred- ibly fast acquisition times but is limited in ultimate resolu- tion by the diffraction limits of visible light. This physical limitation means that any feature below around 200 nm will not be resolved. Laboratory based x-ray microscopy and computed tomography systems can achieve an image resolution of down to 50 nm but maintain excessive acquisition times. Ptychographic x-ray tomography can resolve features below 15 nm, but also requires exces- sive acquisitions times and synchrotron x-ray sources. [6] Scanning probe techniques, such as atomic forcemicros- copy, can achieve a resolution down to the atomic level, but the incredibly long acquisition time required to image an ICwouldmake this a very poor choice. Thebest imaging tool to use for ICdecomposition and assurance is the SEM. The combination of sub nanometer resolutions coupled with relatively fast scanning times make this the ideal choice for imaging the full die area of a target layer. FEATURE EXTRACTION AND POLYGON GENERATION After the full mosaic of each layer has been captured, the features across the entire layer are converted from pixels into vectorizedpolygons. This is conductedby using a diverse array of pixel transformation processes, neural networks, [7,8] thresholding filters, [9] smoothness filters, and other morphological operations. [10,11] The extracted polygon features are the metal traces, interlayer connec- tion vias, transistor gates, andactive implant regions of the design layout. By accurately recovering all these features across every layer, one effectively creates an as-fabricated full design stack-up that cannowbe compared to the origi- nal golden reference design layout. As an example of the imaging and polygon extraction process, a detail image of the SPI module from Fig. 2 is depicted in Fig. 4. The full SPI region depicted in Fig. 4a was stitched together from an 8 by 6 image array to create the full mosaic image of the region of interest. Figure 4b is the zoomed in region of the red rectangle in Fig. 4a where individual features are made visible. The resulting vectorized polygons are displayed in Fig. 4c. Fig. 4 (a) Scanning electron micrograph of the SPI region M1 layer of a 130 nm node SRAM device. (b) The red box zooms in to see individual features. (c) The resulting extracted vectorized polygons (green) are overlaid on the imaged features.