February_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 23 NO. 1 14 selection allows material interfaces to be used as an etch stop. [1] This is the most inexpensive method, however, it creates hazardous waste from the etch materials. Dry etching uses plasma for selective, repeatable, and anisotropic material removal in a highly controlled environment. The tools for dry etching are much more expensive than for wet etching but provide the ability to etch off material with tens of nanometer accuracy. Mechanical milling and CMP are similar, but distinct. Milling is non-selective and can remove material from targeted regions. Aligning a sample to be perpendicular to the milling bit is straightforward, however, milling struggles with uniformmaterial removal over large areas. By contrast, CMP offers planar, semi-selective material removal. Provided the correct pad and polishing media are used, material will remove very evenly across the entire surface. The sample, however, must be perfectly flat to the platen to avoid removing material in a wedge shape. This presents a significant problem for integrated circuit samples as thewedge tends tocausemultiple layers of the chip die to be exposed at once. Additionally, CMP requires the most operator skill, yet maintains the lowest repeatability. As an example, a serial peripheral interface (SPI) module integrated onto a 130 nm static random access memory (SRAM) chip was delayered so that every layer (7 metal, 7 via, polysilicon, and active layers) could be imaged with a scanning electron microscope (SEM). CMP was used to polish material down dielectric material to themetal interconnect layers. Then, themetal layerswere wet etched away using acids selective to the metal. This process was repeated until all the layers were imaged and removed down to the polysilicon layer, shown in Fig. 2. After imaging the polysilicon, the remaining circuit was wet etched away leaving the final layer, active silicon, to be imaged. The challenges of sample preparation in the integrated circuit assurance context largely revolve around the range of different approaches that exist toaddressing the various delayering problems one encounters in practice. Certain techniques tend to lend themselves better in certain scenarios, but they all have limitations and drawbacks that make choosing an optimum approach or technique unclear. Process variation, the lab environment, and even technical skill or experience have dramatic impacts on things such as precision and repeatability, whichmakes IC Fig. 2 Serial peripheral interface (SPI) module on 130 nm SRAM chip delayered with chemical mechanical polishing and wet etching to expose the polysilicon layer. Fig. 3 Iterative process of imaging and sample delayering until all target layers have been processed and imaged.