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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 23 NO. 1 12 APPLIED FAILURE ANALYSIS TOOLS AND TECHNIQUES TOWARD INTEGRATED CIRCUIT TRUST AND ASSURANCE Adam G. Kimura, 1 Adam R. Waite, 1 Jonathan Scholl, 1 and Glen D. Via 2 1 Battelle Memorial Institute, Columbus, Ohio 2 Air Force Research Laboratory, Dayton, Ohio kimura@battelle.org EDFAAO (2021) 1:12-18 1537-0755/$19.00 ©ASM International ® INTRODUCTION Over the last couple of decades, the semiconductor industry has made dramatic strides in advancing process node technology as well as increasing design complexity. Market pressures have pushed designers into utilizing more third-party intellectual property (IP) to reduce the time-to-market for microelectronics. In a similar fashion, economics have driven the growth of the semiconductor industry to an international scale, creating a complex global supply chain for microelectronics design and manufacturing. These trends have introduced new vul- nerabilities into the design and fabrication lifecycle that present significant trust issues as it relates to the assur- ance of manufactured chips. THE MICROELECTRONICS TRUST AND ASSURANCE PROBLEM In today’smicroelectronicsmarket, some of the critical questions being raised are: For a given chip, is it authentic or counterfeit? Will the chip function exactly as intended throughout the life of its deployment? Has anythingmali- cious been inserted into the design that would compro- mise the system it will be integrated into? These questions are critical to ask yet remain extremely difficult to answer. Process nodes are approaching 5 nm and beyond while the number of devices on a single chip has increased to billions of transistors. Traditional post-fabrication testing procedures are simply not enough to cover the full verifica- tion space when trying to arrive at a confidence level of assurance of an untrusted chip. Furthermore, traditional verification processes are one dimensional, typically veri- fying functionality and operating specifications only, and donot provide a holistic assessment of the full design. As a result,many of the supply chain trust concerns are difficult to address with traditional post-fabrication assessments. This gap in current verificationandvalidationpractices has coalesced researchers towarddeveloping new techniques for determining assurance of integrated circuits (IC). Many of these tools and techniques historically have been used in failure analysis applications, however, the assurance community has found these same tools tobe instrumental toward developing the methods and processes to assess the assurance of untrusted ICs. THE UNTRUSTED FOUNDRY THREAT When an IC design layout is sent to the foundry for manufacturing, designers typicallyhavenoway toobserve the manufacturing process. This creates a trust problem with the manufactured chips as there is no clear path for evaluating the integrity of the supply chain and fabrica- tion process. The designer is left with only a blind trust in the component’s integrity. For critical systems these components are embedded into, blind trust is not good enough. Many of these systems demand highest levels of assurance because the associated risk of system failure could have catastrophic implications. As such, develop- ing the framework and methods to arrive at quantifiable levels of assurance is crucial for achieving objective levels of confidence in untrusted components. QUANTIFIABLE ASSURANCE OF MICROELECTRONIC DEVICES IN A ZERO TRUST ENVIRONMENT After adesignmoves beyond the graphic design system II (GDSII) layout stage and into manufacturing, there is no longer a golden design reference to correlate to for