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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 22 NO. 3 6 region (fin). Figure 8 shows the plan view TEM image of the defect. The sample was submitted for cross-section TEMand plan-viewTEM, however these techniques alone werenot able tohelp the responsible integrationengineers understand the root cause of the failure. The sample was later submitted for tomography TEM, which clearly showed the root cause of the failure is due to amissing/etched out region of fin that has been backfilled with gatematerial. Figure 9 is the tomography TEM image showing the root cause as fin etch out. CONCLUSIONS Semiconductor failure analysis for advanced tech- nology nodes beyond 14 nm has become increasingly challenging for engineers and analysts working with tra- ditional approaches to defect classification, particularly in memory applications. In some cases, the defects are simply too subtle to resolvewith existing SEM instruments currently on themarket, or the defects themselves require more qualitative data than SEMor even conventional TEM analysis can provide. The three case studies examined in this article have demonstrated how the classic memory failure analysis methodologies of progressive FIB cross- sectioning and top-down analysis can be supplemented using the advanced techniques of nanoprobing and TEM tomography to fully understand thenatureof these elusive physical failure mechanisms. ACKNOWLEDGMENTS Thisworkwas performed at GlobalFoundries Inc., New York. The authors would like to sincerely thank the efforts of Anthony Taylor, BrianMulvaney, Nicolas LaManque, and EdwardMolinaof theElectrical FailureAnalysis (EFA) team, and the Physical Failure Analysis (PFA) team for their TEM analysis support. REFERENCES 1. J-Y Glacet and F. Lee: “Embedded SRAM Bitmapping and Failure Analysis for Manufacturing Yield Improvement,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2000. 2. C.Q. Chen, G.B. Ang, P.T. Ng, A.C.T. Quah, H.P. NG, Angela, J. Lam, and Z.H. Mai: “Non Visible Defect Analysis by the Nanoprobing Methodology,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2005. ABOUT THE AUTHORS Noor Jehan Saujauddin , was awarded her bachelor’s in elec- tronic engineering by the University Technology of Malaysia. She was a failure analysis staff engineer for ten years at Silterra Malaysia. From Silterra, she joined the technical staff at GlobalFoundries in Malta, New York as a failure analyst for seven years. She is now a senior development engineer, focusing on nanoprobing at Carl Zeiss PCS, Pleasanton, California. Fig. 7 Defect captured from a FIB cross-section image. Fig. 8 Plan view TEM of the defect at gate level. Fig. 9 Tomography TEM showing fin etch out.