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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 22 NO. 3 4 EDFAAO (2020) 3:4-7 1537-0755/$19.00 ©ASM International ® SRAM PHYSICAL FAILURE ANALYSIS CHALLENGES IN TECHNOLOGY NODES BEYOND 14 nm Noor Jehan Saujauddin, 1 Kevin Davidson, 2 and Esther P.Y. Chen 2 1 Zeiss Group, Pleasanton, California 2 GlobalFoundries Inc., Malta, New York jehan.saujauddin@zeiss.com INTRODUCTION In the complex world of semiconductor failure analy- sis, many unique challenges have arisen as a result of the continuous downscaling of technology nodes. Of particu- lar interest to failure analysis engineers is the ability to determine the root cause of defect mechanisms that may have physical characteristics beyond the imaging resolu- tion limits of current scanning electronmicroscopy (SEM) toolsets. In these particular situations, itmay be necessary to rely on advanced characterization techniques to help supplement the traditional SEM approach. Historically, semiconductor failure analysis labs have relied heavily on the use of various SEM and focused ion beam (FIB) toolsets to perform tasks that enable high- throughput classification of defects present in memory products. The standard methodology employed by the majority of high-volume labs involves the use of a full wafer dual beam system (SEM + FIB) where automated navigation is used to locate a particular failing cell, and progressive FIB cross-sectioning is performed through the cell with SEM images captured at regular intervals. This approach allows for relatively simple physical characterizationof anentire static randomaccessmemory (SRAM) bitcell, for example, when images are timed to capture each relevant transistor node of the cell. Another method by which memory failure analysis is performed is the classic “top-down” approach, which relies on manual sample deprocessing and manual array count- ing to find the failing bit of interest. In both methods, for the vast majority of “hard” defects that cause a total electrical failure across all biasing conditions, the physi- cal defect responsible is visually resolved with relative ease. However, there are instances where certain defects can cause electrical fails and yet the root cause physical mechanismcannot beascertained fromthe corresponding suite of SEM images. The following case studies present three situations where advanced characterization tech- niques were able to supplement the classic approaches to failure analysis in memory products. CASE STUDY #1: ABNORMAL GATE PROFILE A single-cell failure with a triangular pattern on a wafer was submitted for failure analysis. The first attempt used a traditional method. FIB cross section was directly Fig. 1 FIB cross section image is inconclusive with regards to defect confirmation. Fig. 2 Nanoprobingwas used to confirmthe failure electric- ally; data shows some V t shift on the pull down transistor and thus validates the fail.