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edfas.org 29 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 22 NO. 2 3D HOT-SPOT LOCALIZATION BY LOCK-IN THERMOGRAPHY Sebastian Brand and Frank Altmann Fraunhofer Institute for Microstructure of Materials and Systems IMWS, Halle, Germany sebastian.brand@imws.fraunhofer.de EDFAAO (2020) 2:29-35 1537-0755/$19.00 ©ASM International ® INTRODUCTION Today’s package developments including system in package (SIP) approaches, wafer level packaging (WLP), chip embedding, and 3D heterogeneous integration are considered a determining factor for continuous innova- tion in microelectronics. [1] With respect to 3D integration, the through-silicon via (TSV) interconnect technology has rapidly attracted attention for high-density, vertical- system integration concepts. Non-destructive failure localization techniques take a key role for successful and efficient root-cause analysis, particularly for advanced 2.5D and 3D packaging architectures including stacked dies and TSVs. [2] Microscopic lock-in thermography (LIT) [3] represents a promising candidate for electrical defect localization within 3D packages exemplarily shown in Fig. 1. The tech- nique allows to non-destructively localize resistive opens and electrical shortswithinpackageddevices by detecting and analyzing defect-related thermal sources caused by the dissipation of electrical power. Current LIT systems are based on direct thermal imaging techniques in combination with a two-phase, lock-in amplification as illustrated in Fig. 2. In Fig. 2, the investigated specimen is electrically stimulatedby apower source. The stimulation, however, is repeated at a fixed repetition rate, which is referred to as the lock-in frequency. The periodic excitation of a resistive defect will lead to a periodically pulsating hot-spot. At each pixel of the cameras de- tector, a transient signal with the duration of a lock-in period is ob- tained.Thesesignalsarefurthercor- related to a sine signal and a cosine signal that are synchronized to the electrical excitation of the sample. This approach allows for the detection of temperature gradients in the μ-Kelvin range at a spatial resolution of below 5 μm. A profound description of the fundamentals of lock-in thermography can be found elsewhere. [3] The heat, generated upon the dissipation of electrical power within the defect propa- gates through the IC stack and the packaging materials until it reaches the device surface. At the surface, this thermal energy forms a hot-spot fromwhich it radiates off as infrared waves that can be detected by an IR-sensitive Fig. 1 Example of a complex 3D package: Cross-sectional viewof a DRAMmemory devicewith TSV and μ-bump interconnects. Fig. 2 Principle of lock-in thermography (LIT).