May_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 22 NO. 2 28 on SOI based devices, which are difficult to find by conventional top-down (PVC) and cross-sectional imaging methods. While the SCM data cannot definitively show that the fails are resistive vs. open, it can be used to help isolate these de- fects for further nanoprobing or TEM analysis and can give some insight into the severity of the fail/magnitude of the contact resistance. ACKNOWLEDGMENTS This work was performed at Global- Foundries Inc., Malta N.Y., USA. The authors would like to sincerely thank Satish Kodali for thoughtful discussion. The authors would also like to thank Anthony Taylor for his contributions to the analysis. REFERENCES 1. L. Liu, Y. Wang, H. Edwards, D. Sekel, and D. Corum: “Combination of SCM/SSRM Analysis and Nanoprobing Technique for Soft Single Bit Failure Analysis,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2004. 2. L.C.T. Sheridan, T. Schaeffer, Y. Wei, S. Kodali, and C.K. Oh: “Die-Level Scanning Capacitance Microscopy Fault Isolation on SOI Fin-FET Devices for Advanced Semiconductor Nodes,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2018 . Fig. 9 Nanoprobingdata (saturation regime) for three transistorswithone resistive contact all show asymmetric behavior 3. L.S. Huat, L. Hnin-Ei, V. Narang, and J.M. Chin: “Scanning Capa- citance Microscopy for Failure Analysis of SOI-based Advanced Microprocessors,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2010. 4. S.P. Hong, Z.X. Hua, C.K. Chung, andA. Chin: “Applicationof Scanning Capacitance Microscopy on SOI Wafer in Die-Level Failure Analysis,” IEEE Int. Symp. Phys. Failure Anal. Integr. Circuits, 2014 . 5. S. Pendyala, D. Albert, K. Hawkins, and M. Tenney: “dC/dV and CV Characterization of Gate Resistance Defects in eDRAMCircuits,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2013. ABOUT THE AUTHORS Lucile Teague Sheridan is a chemist with over 20 years experience using scanning probemicros- copy techniques specifically focused on semiconductors. Her career has included positions in both research and industrial settings. Her prior affiliations include Trinity College Dublin, NIST, Savannah River National Laboratory, AMD, and GlobalFoundries. At present, Dr. Sheridan is a product engineer at Wolfspeed working with Power MOSFETs. She earned her B.S. from Western Carolina University and a Ph.D. from the University of North Carolina at Chapel Hill. Don Nedeau is a failure analysis engineer who has spent the last nine years withGlobalFoundries inMalta, NY. Much of his experience iswith electrical failure analysis onmemory devices and using dual beam SEM/FIBS for a variety of FA techniques. Nedeau studied physics and mathematics at SUNY Albany. Visit the Electronic Device Failure Analysis Society website edfas.org COMBINED SCM AND NANOPROBING STUDY OF RESISTIVE FAILS (continued from page 25)