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edfas.org 23 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 22 NO. 2 fail was due to a BEOL defect. Instead, the fail signaturewasmost likely due to a FEOL or MOL issue. Therefore, it was determined that direct, progressive FIB cross-sectional imaging into the AOI as described above, would be the fastest method to determine the physical root cause of the fail. Because multiple bits were impacted, it was expected that this would be a very straight-forward analysis with the defect being quite obvious in the cross-sectional images. This, however, was not the case. No defects were observed in the entire cluster area during progressive cross- sectional imaging. TOP-DOWN INSPECTION METHODS AND SCM Top-down, layer-by-layer analy- sis was then performed at a second cluster fail location. Layer-by-layer SEM imaging didnot yield any BEOL fail signature in the AOI. The sample was then polished to contact level for SCM imaging as a quick method for confirming the fail location. SCM imaging has been routinely utilized in logic and SRAM for die-level fault isolation of fails on SOI technologies. [1-5] Figure 2 shows the SCM data (a) and layout (b) of the cluster defect. Multiple n -type field-effect transistor (nFET) contacts within the AOI have either diminished or show no SCM signal. This lack of SCM signal could be due to a number of different types of fails including active opens, or some sort of dopant issue. Given the gross nature of the defect, if it was due to an active open, such as an unlanded contact or missing epi, this would have been obvious in the FIB cross sectional images (Fig. 3). NANOPROBING In order to determinemore about the nature of the fail, all of the transistors in three of the failing bits (shown in yellow in Fig. 4a) were nanoprobed. A passing bit outside of the fail areawas also probed as a reference. For simplic- ity, this review focuses on the nFET data (pass gates (PGs) and pull downs (PDs) for bits 2 and 3 (Figure 4c-f). Similar results were observed for bit 1. In all plots, the failing transistor is shown in red, the passing transistor is shown in green, and a reference tran- sistor is shown inblack. For each set of data, one transistor shows Idsat that is as much as two orders of magnitude Fig. 2 (a) SCM image (3V AC, 0V DC) and (b) Layout. Failing bits in the cluster are shaded in red. Fig. 3 X-direction FIB cross section SEM image through cluster fail area does not show any obvious defect such as missing epi or unlanded contact. lower than the passing and reference transistor, indicating a resistive contact. The symmetric nature of the forward and reverse bias curves for three of the nFETs shown in Fig. 4c, e, and f indicate a resistive issue in both the source and drain contacts, however, some asymmetric behavior is observed in Fig. 4d, inset, and is discussed later in the article. No abnormal behavior was observed for the pFETs in either of the failing bits (Fig. 5a-b) compared to the reference. This gives us more insight into the nature of the fail. Examining the layout shown in Fig. 4b, it is seen that the gate contact for the pFETs also connects to an active contact for both nFETs and pFETs, depending on the geometry of the individual transistor probed. If the root cause of the fail was associated with a resistive gate contact at this location, abnormal transistor behavior would be seen in pFETs and nFETs alike. Therefore, the nanoprobing data suggests that the resistive fail is isolated to the active contacts (contact layers 1 and 2). CORRELATING NANOPROBING AND SCM DATA In cell 3, there is a slight asymmetric behavior that was observed for the failing PG compared to that of the failing PG in cell 2 (Fig. 6, ~1µA difference in Idsat between forward and reverse vs. ~0.2µA difference). (b) (a)