May_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 22 NO. 2 22 COMBINED SCM AND NANOPROBING STUDY OF RESISTIVE FAILS ON SOI FINFET DEVICES Lucile C. Teague Sheridan and Don Nedeau GlobalFoundries Inc., Malta, New York donald.nedeau@globalfoundries.com EDFAAO (2020) 2:22-28 1537-0755/$19.00 ©ASM International ® INTRODUCTION Scanning capacitance microscopy (SCM) and nano- probing techniques are key tools for isolation and under- standing of the electrical nature of transistor level fails. Several studies have shown that the two techniques are complementary to one another. [1] SCM is particularly useful for silicon-on-insulator (SOI)-based technologies in which other common analysis techniques such as con- ductive atomic force microscopy (CAFM) and scanning electronmicroscopy (SEM) passive voltage contrast (PVC) methods are either not possible (CAFM) or more complex (PVC). [2] A case-study is presented utilizing both SCM and nanoprobing to understand transistor level fails on SOI- based finFET technology at the 14 nm node. An excursion wafer showing an elevated count of cluster-type SRAM defects was sent for failure analysis to determine cause of the fails. These clusters were random in shape and size, often includingmultiple bits inmultiple rows. Usually, analysis of defects of this size is fairly routine using either SEMtop-down inspectionmethods or focused ion beam (FIB) cross-sectional imaging. However, in this case, the analysis was not so straight forward. To that end, this article describes how a combination of analysis methods was used to determine the electrical nature of the fails. In particular, the discussion will focus on the relationship between the SCMand nanoprobing data, and the significance of these findings with respect to failure analysis of SOI technologies in general. CONVENTIONAL SRAM ANALYSIS METHODS Failure analysis for hard fails in SRAM array can be accomplishedusing dual beamfocused ionbeam(DB-FIB) tools with CAD navigation capability. In thismethod, a file with the GDS coordinates of the failing bits is loaded into the CAD software, which is subsequently linked with the DB-FIB tool. Simply put, this allows the analyst to drive to each failing location with high accuracy to perform sequential cross-sectional imaging of the failing bit. As the analyst slices thru the area of interest (AOI), they are able to easily locate the physical root cause of the fail. This methodology is best utilized for single bit fails, double bit fails, andother small clusters as these fails 1) allow for high resolution imaging and 2) are typically due to front end of line (FEOL) andmiddle of line (MOL) defects below the first metal layer. Larger defects, such as bit line (BL) and word line (WL) fails are not suitable for this type of analysis as the cause of the fail can occur anywhere in the BL, WL, or periphery and may occur in one of many back end of line (BEOL) layers. FIB CROSS-SECTION In the case presented here, the unusual shape of the cluster fails (Fig. 1) suggested a low probability that the Fig. 1 Example bitmap image of a cluster fail. Each box represents a memory cell. Each shaded box represents a failing cell in the cluster.