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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 22 NO. 2 2 PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/Nova Measuring Instruments nicholas-a@novameasuring.com Scott D. Henry Publisher Mary Anne Fleming Manager, Technical Journals Kelly Sukol Production Supervisor Joanne Miller Managing Editor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant David L. Burgess Accelerated Analysis Jiann Min Chin Advanced Micro Devices Singapore Edward I. Cole, Jr. Sandia National Labs Szu Huat Goh GlobalFoundries Singapore Ted Kolasa Northrop Grumman Innovation Systems Rose M. Ring Howard Hughes Research Lab LLC David Su Yi-Xiang Investment Co. Sam Subramanian NXP Semiconductors Paiboon Tangyunyong Sandia National Labs Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is pub- lished quarterly by ASM International ® , 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org.Copyright©2020byASMInternational.Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $150 U.S. per year. Authorizationtophotocopy itemsfor internalorpersonaluse, orthe internalorpersonaluseofspecificclients, isgrantedby ASM Internationalfor librariesandotherusersregisteredwith theCopyrightClearanceCenter(CCC)TransactionalReporting Service, provided that the base fee of $19 per article is paid directlytoCCC,222RosewoodDrive,Danvers,MA01923,USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. F ailure analysis (FA) in semicon- ductor packaging is becoming increasingly challenging as a surge of innovation in packaging design yields more complex architectures. At the same time, these archi- tectures have become more critical to the differentiation and success of electronic systems and products. Together, these trends pose a business critical challenge to FA labs to rapidly improve analytical methods in order to resolvemore complex and varied issueswith sustained velocity. In addition to a focus on continuous scientific and technological advancement for analyti- cal tools, FA labs can now also readily make use of artificial intelligence (AI) methods toenhance the capability andproductivity ofmany existing tools and methods. Opportunities exist across the analysis landscape: within low yield analysis (LYA) for metrology and disposition of test failures, and within FA for electrical fault isolation (FI), nondestructive physical analysis, and material spectral analysis. Targeted use of AI can accelerate metrology, reduce the number of failures that require FA, and accelerate FI and FA process flows. Collectively, these methods can provide FA labs with critical capabilities to support the development and qualification of these innovative new packag- ing architectures. The opportunity begins in reducing the number of failures requiring full electrical fault isolation and failure analysis (FI/FA). It is common to reduce FI/FA workload by using signature binning of failures, where a distinct physi- cal failuremode, repeatedly discovered and confirmed by FI/FA, is correlated with a distinct electronic test signal (e.g., pass/fail rating for a single electrical test structure). Once well correlated, these fails can bypass the FI/FA process because the root cause is already understood. However, this clear and direct relationship between electrical testing and physical failure mode can break down with more complex packaging when test structures are unable to provide 100% coverage on internally confounded electrical structure fail- ures. While these cases can result in larger workloads for time consuming FI/FA, there is also opportunity to use machine learning (ML) tools to assign confidence levels to various potential failuremodes based on aggregation of known testing data and known historical use or stress. In addition to enabling correlation of aggregated, disparate testing data streams (e.g., electrical test results plus physical metrology screening data), ML also can better use the complexities of the data streams (e.g., raw values of test data rather than threshold rule based pass/fail inputs or raw image data for a physical defect MAY 2020 | VOLUME 22 | ISSUE 2 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL ARTIFICIAL INTELLIGENCE PROVIDES OPPORTUNITY FOR FAILURE ANALYSIS William Hammond and Deepak Goyal, Intel Corporation edfas.org (continued on page 13) Hammond Goyal