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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 22 NO. 2 12 ABOUT THE AUTHORS Fauzia Khatkhatay earned her doctorate degree from Texas A&M University and her bachelor’s andmasters’s degrees fromLouisiana TechUniversity, all in electrical engineering. Her doctoral thesis focused on functional ceramic thin filmdeposition and characterization. Her professional experience includes photolithography, CD-SEM metrology, and inline defect reduction. She was most recently affiliatedwith GlobalFoundries Inc. located inMalta, N.Y., as a principal engineer in failure analysis. Pradip SairamPichumani studied polymer engineering in India and earned his master’s degree in the field of material science and engineering from the University of Texas, Arlington. He has been working in the field of fault isolation and failure analysis for six years. He is currently a principal engineer - complex analysis at GlobalFoundries Inc., Malta, N.Y., where he specializes in IC package failure analysis and serves as the technical lead and point of contact for customers. can be significantly increased. Polishing time reduction has been confirmed using epoxy pucks with and without impregnated samples. The incorporation of conductive epoxy into themodified puckminimizes charging artifacts and image distortion during SEM analysis. Inserting the sample into a slot in the modified puck and stabilizing it withmountingwax yields a similar polishing finishwith the ability to easily remove the sample from the puck, com- pared to samples directly embedded in epoxy. In terms of polishing time, all iterations of themodifiedpuck are com- parable, with a polishing time reduction of at least 84% compared to a conventional puck. While the improvement has been quantified only in terms of polishing time, it is expected that theremust be a comparable reduction in the usage of polishing consumables like sandpaper, polishing cloths, and slurry, because lessmaterial is being polished. Futurework includes: (1) optimizing the dimensions of the outer ring and central rib relative to the dimensions of the sample, (2) optimizing the composition and density of the conductive epoxy sections, and (3) exploring othermount- ing agents whosematerial propertiesmore closelymatch that of the epoxy puck to stabilize the sample in the epoxy slot. This simple and practical, yet very effective design and its iterations can help failure analysis labs reduce cycle-time, improve SEM image quality, and offer flex- ibility for further analysis for mechanical cross-sectioned semiconductor package samples. ACKNOWLEDGMENTS The authors would like to thank Christopher Torcedo and Russell Farr for their assistance with mechanical polishing. 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