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edfas.org 57 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 4 GUEST EDITORIAL CONTINUED FROM PAGE 2 Data courtesy of WikiChip. development to identify new solutions internally, often partnering with equipment vendors, consortia, or uni- versities. Many of these ideas were published, patented, or spun off into small businesses that offered innovative solutions available to anyone in the community. Today, with as few as three companies owning bleeding edge CMOS logic fabs, there is a drastic decrease in the number of independent failure analysis organizations observing and contributing to the development of solutions to prob- lems of an ever-growing complexity. Many companies are choosing to rely on the foundry itself for failure analysis and have significantly reduced the scale of their failure analysis labs—or closed them altogether—thereby con- centrating reliance on fewer and fewer resources. During recent years, we have also observed a consoli- dation of many equipment vendors, which I speculate is correlatedwith the reduction in companies buying equip- ment inmanyof thebleeding edge categories. This smaller business space and consolidation are estimated to create a net reduction in overall failure analysis research and development funding compared to normalized historical value. Additionally, with fewer sales opportunities there may also be a negative effect resulting in cost increases for newly developed equipment, which may be beyond reach for many. Historically, consortiums such as SEMATECH main- taineddedicated councilsworking inparallel to ensure the failure analysis ecosystemwas both aware andaddressing upcoming challenges. These types of consortia encour- aged companies, vendors, and the failure analysis com- munity toaddress challenges theymaynot haveotherwise considered. Unfortunately, focus on such activities has dwindled in recent years with the changing environmen- tal landscape. EDFAS and ISTFA leadership are working to address these perceived gaps by kicking off activities to create and refine a ranked gap analysis list and open discussion venues with the community. In the future, it is expected that these activities will be integrated into the annual ISTFA event and may grow into a dedicated technol- ogy roadmap session or panel. ISTFA 2019 will include technology roadmap content at the beginning of each user group session in the form of a “top five concerns” discussion and offer the community a chance to provide input. I hope everyone has an opportunity to attend and join the conversation. ABOUT THE AUTHOR Ryan Ross is the group supervisor of the Analysis and Test Laboratory at NASA’s Jet Propulsion Laboratory in Pasadena, Calif. He currently serves as secretary of the EDFAS Board of Directors and previously served on SEMATECH Integrated Circuit and Packaging Failure Analysis Councils.