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edfas.org 37 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 4 MOL TDDBwill be themore stringent one for next genera- tion nodes, such as 7 and 5 nm. Not only will newmateri- als and architectures need to be explored, a more robust process control also will be required. REFERENCES 1. A.E. Islam: “Current Status of Reliability in Extended and Beyond CMOS Devices,” IEEE Trans. Dev. Maters. Reliab., 2016, 16 (4), p. 647-666. 2. C. Hu, S.C. Tam, F-C Hsu, P-K Ko, T-Y Chan, and K.W. Terrill: “Hot- Electron-Induced MOSFET Degradation—Model, Monitor, and Improvement,” IEEE Trans. Electron Devices, 1985, 32 (2), p 295. 3. M.G. Ancona, N.S. Saks, and D. McCarthy: “Lateral Distribution of Hot-Carrier-Induced Interface Traps inMOSFETs,” IEEE Trans. Electron Devices, 1988, 35 (12), p. 2221-2228. 4. G. Chen, M.F. Li, and T. Jin: “Electric Passivation of Interface Traps at Drain Junction Space Charge Region in p-MOS Transistors,” Microelectron. Reliab., 2001, 41, p. 1427-1431. 5. D.J. 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R. Ranjan, S. Uppal, H. Yu, B. Parameshwaran, T. Nigam, A. Kerber, C. LaRow, and M.I. Natarajan: “Impact of e-SiGe S/D Processes on FinFET PFET TDDB Reliability,” IEEE Electron Devices Technology and Manufacturing Conference (EDTM), 2017, p. 20-22. 24. E.Y. Wu, B. Li, J.H. Stathis, andC. LaRow: “Time-Dependent Clustering Model versus Combination-BasedApproach for BEOL/MOL and FEOL Non-UniformDielectricBreakdown:SimilaritiesandDisparities,” IEEE Int. Reliab. Phys. Symp. (IRPS), 2014, p. 5B.2.1-2.7. 25. K. Yang, T. Liu, R. Zhang, and L. Milor: “Circuit-Level Reliability Simulator for Front-End-of-Line andMiddle-of-Line Time-Dependent Dielectric Breakdown in FinFET Technology,” IEEE 36th VLSI Test Symposium (VTS), 2018. 26. T. Shen, K.B. Yeap, S. Ogden, C. Christiansen, and P. Justison: “New Insight on TDDBArea ScalingMethodology of Non-Poisson Systems,” IEEE Int. Reliab. Phys. Symp. (IRPS), 2018, p. P-GD.1-1-P-GD.1-6. ABOUT THE AUTHOR Xinggong Wan was born in Anhui Province, China. He received his bachelor’s degree in applied physics fromAnhui University in 1995. In 1998, he obtained anM.S. in condensedmatter physics from the Institute of Solid State Physics Academy, Hefei, China. In 2001, Wan received a Ph.D. in materials science fromFudanUniversity, Shanghai. From2001 to 2004, hewaswith the Shanghai Huahong-NEC Electronics Company (HHNEC) andworked as a semiconductor device reliability engineer. From2002 to 2003, he was assigned to IMEC in Leuven, Belgium, where he was involved with the characteriza- tion of reliability of gate dielectrics for sub-100 nm CMOS technologies. From 2004 to 2008, he was a technologymanager in charge of a reliability failuremechanismstudy at the Shanghai IC R&D Center (ICRD). From. 2008 until 2011, Wan worked for Chartered Semiconductor in Singapore, and is now with GlobalFoundries in Malta, N.Y., working as a manager of reliability engineering on reliability risk management in advanced CMOS nodes. He has co-authored over 30 papers for journals and conferences.