November_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 4 36 time-to-breakdown (TBD) clearly showed that regardless of transistor type, electron injection will result in shorter TBD than that of hole injection. This also matches what C. Yang et al. reported. See Fig. 11. Therefore, n-FinFET would be most critical for the TDDB failure mechanism and should be taken care of for further scaling down technologies. The above study only considered pure gate stack im- pact on the TDDB performance. However, the lateral source/drain (S/D) would also have a significant impact on TDDB degradation. R. Ranjan et al. [23] reported an S/D e-SiGe process impact on TDDB on p-FinFETs, as shown in Fig. 12. It is observed that a thicker e-SiGe buffer layer im- proves the p-FinFET TDDB. Electrical andphysical analysis revealed that with a thinner buffer layer, Ge atoms will migrate into gate dielectric and accelerate the break- down mechanisms due to poor surface roughness and stoichiometry. In addition, the process optimization of pre-baking of the e-SiGe trench canalso improve the TDDB even for a relatively thinner buffer layer. Therefore, S/D engineering is not only necessary for device targeting and HCI reliability optimization, but also must be considered proactively for the TDDB failure mechanism. Another source of dielectric breakdown between the gate and S/D is the so called middle-of-line (MOL) TDDB. [24-25] This type of breakdown happens at the dielec- tric between the gate and contact metal stud. See Fig. 13. MOL TDDB is drawing more and more attention on the advanced FinFET technology nodes due to the trade-off between amore aggressive gate-to-contact pitch and the process capabilities. MOL process challenges can be categorized into two issues: 1) local variations such as line edge roughness (LER), linewidth roughness (LWR), and local critical dimen- sion non-uniformity (CDU); and 2) within-wafer (WiW) and wafer-to-wafer (WtW) variations, such as overlay control, dielectric thickness uniformity, and chemical mechanical planarization (CMP) uniformity. Statistical data analysis can be difficult because both WiWandWtWcouldmakeWeibull distribution convoluted with systematic variations. T. Shen et al. [26] observed a non-Poisson area scaling behavior where early failure sites were systematically distributed. They proposed a revised area scalingmethodology consisting of scaling to the reticle area by using different area test structures, and then scaling back to the product chip areawith the ratio of the product area to reticle area. The chip-to-chip variation was de-convoluted and theWeibull statisticswithPoisson area scaling were restored within each chip. Therefore, overly pessimistic results could be avoided by considering all variations holistically andmaking a lifetime projection. CONCLUSION Device reliability challengeswerediscussed frommany perspectives, such as implantation tuning, annealing temperature, and characterization methodology. The 3D nature of FinFET must be considered to improve intrinsic reliability. Among all failuremechanisms, gate dielectric/ Fig. 11 TDDB distributions of inversion and accumulation states between n-FinFET and p-FinFET. Fig. 12 2Dschematics of p-FinFETs deviceswithe-SiGebuffer layer engineering. Fig. 13 Illustrationof gate-oxidebreakdown (GOBD) andMOL TDDB. Purple dashed box: Location of GOBD. Blue dashed boxes: Locations of MOL TDDB.