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edfas.org 35 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 4 degradation than a thinner fin. The hypothesis was that a thinner fin has a higher vertical electrical field causing more holes to be injected into HKMG and generates more bulk traps. See Fig. 8. P. Srinivasan et al. reported a FinFET (<=14 nm) HKMG layer post deposition anneal (PDA) temperature depen- dence of NBTI degradation. [18] They observed that higher PDA temperature resulted in better NBTI degradation, as shown in Fig. 9. X-ray diffraction (XRD) analysis showed that the higher PDA temperature would make IL thicker and more crystalized HKMG. These are two beneficial factors to improve NBTI. However, the PDA temperature could not be increased very aggressively. The tuningwindow is actually very small due to the device performance trade-off. With FinFET further scaling down, this knobmay no longer be relevant. TIME-DEPENDENT DIELECTRIC BREAKDOWN Time-dependent dielectric breakdown (TDDB) has been studied comprehensively on the planar MOSFET. The characterization method, data analysis modeling, and failure mechanism were intensively discussed by manufacturing companies and research institutes. [19] However, compared with planar MOSFET devices, the TDDBbehavior in FinFETwithHKMGhas different features and it is challenging to improve TDDB lifetime. There is still no consensus on whether the HK or IL layer plays a dominant role in TDDB degradation. [20] Again, we need to understand whether the sidewall channel or the fin top channel contributes more to the TDDB degradation. C. Yang et al. [21] reported that the oxygen vacancy created by TDDB stress plays a significant role in TDDB degradation. They observed a very different gate leakage current evolution with time between n-FinFET and p-FinFET, as shown in Fig. 10. During NFET TDDB, the gate was stressed with positive bias. Therefore, electrons will inject from the Si substrate and damage the IL layer and could possibly be trapped in the HK layer. While PFET TDDB is the opposite way, holes will inject from the sub- strate and traps in the IL and HK layers. Due to the poten- tial barrier height difference and different effective mass of electrons and holes, significant differences between NFET and PFET were observed. H. Kim et al. [22] made a further study on the TDDB degradation difference between n-FinFET and p-FinFET. They stressed both n-FinFET and p-FinFET with different polarity, which would result in an inversion state and accumulation state for both n-FinFET and p-FinFET. The Fig. 8 Fin width dependence of subthreshold swing (SS) variation rate (left axis) and drain current degradation rate (right axis) under different NBTI stress voltages. [17] Fig. 9 ∆VT BTI degradation vs. HK PDA temperature for both NFET and PFET. T1, T2, T3, and T4 are PDA temperature, and here T4<T3<T2<T1. Fig. 10 Gate leakage current evolution with time between NFET and PFET.