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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 4 34 should be included in order to get an accurate lifetime out of the HCI test. A. Kerber et al. [12] reported similar findings, concluding that IO PFET HCI is worse than IO NFET HCI. They also characterized ring oscillator (RO) frequency degradation under stress voltage. They concluded that the correlation of RO degradation data with the HCI test on discrete devices reveals there is less reliability margin for IOdeviceswhile for core devices, theDC equivalent HCI lifetime targets can be substantially relaxed. BIAS TEMPERATURE INSTABILITY Bias temperature instability (BTI) is challenging for both planar and FinFET devices. [1] Compared to planar devices, the process integration of FinFET with HKMG is complicated and there are more factors affecting BTI degradation. Ultra-fastmeasurement is needed to capture actual device threshold voltage degradation before it recovers. For the BTI degradation in FinFETs, both NFET and PFET BTI degradation mechanisms need to be con- sidered. NFET positive bias temperature instability (PBTI) degradation is related to electron trapping in the bulk of HKMG, while PFET negative bias temperature instability (NBTI) degradation occurs mostly in the interfacial layer (IL) between the silicon and HKMG layer. [13-14] Therefore, both HKMG and IL are the most critical for BTI degrada- tions. [15] K. Lee et al. [16] summarized theNFET and PFET BTI degradation trend from32 to 14 nmHK/MG technologies. See Fig. 6. Basically, at the 14 nmFinFETnode, NFETPBTI was not degraded much compared to the previous nodes, while PFETNBTI wasmuchworse. Therefore, thebig challenge is how to balance HKMG scaling and NBTI degradation. The first question is whether NBTI is different between the fin top surface with <100> orientation and fin sidewall with <110> orientation. [15] S. Wu et al. reported BTI degradation followed the same law for both planar and FinFET PFET devices, which indicates no additional interface traps for the <110> surface, [16] as in Fig.7. W. Yeh et al. reported a fin width dependence of NBTI behavior. [17] They observed that a thicker fin had less NBTI Fig. 4 ID-VD characteristics: Reductionof drain currentwith increasing fin number (drain current was normalized by fin numbers). Fig. 5 PFET HCI shows stronger dependence on number of fins while NFET HCI shows no dependence. Fig. 6 HK/MG transistor BTI technology trends: 32 to 14 nm generations at five years DC, T=125°C. 14 nm BTI A and B indicate initial and more recent results, respectively. [14] Fig. 7 BTI degradation comparison between planar and FinFET PFET. FASTER AND MORE ACCURATE FAILURE ANALYSIS (continued from page 31)