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edfas.org 31 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 4 implantation scheme to improve HCI without sacrificing device performance. However, it is not straightforward to achieve an optimal junction profile on FinFET devices due to 3D channel formations. TCAD simulation has always been a beneficial tool to characterize the junction profile and improve HCI degradation. However, the simulation platform must be calibrated based on a significant amount of silicon data. From the TCAD simulation results, it is clear that solving an HCI issue could be done by increasing the implanta- tion energy to carve the junction deeper into the silicon. Therefore, the maximum impact ionization location is to go deeper into the siliconwith less impact on the channel. However, it turns out that getting too aggressive with the energy level could penetrate the gate material and leave a counter-doped channel near the source/drain side. In this case, short channel NFET devices would see a sig- nificant increase in off-state leakage. The other tuning knobs would adjust implantation energy, angle, and dose. Finding the most optimal condition requires a lot of silicon and research time to complete the processing using multiple variables within the experiments. Figure 2 shows ourworkon trying toachievea less than optimal impact ionization condition called “Scheme B” by skipping lightly-doped-drain (LDD) implantation in order to increase device performance. Scheme B should cause impact ionization to occur deeper in the silicon compared to the conventional scheme “with LDD.” Scheme B should also allow optimal device drive current performance to be maintained. Results are promising based on consistent and statis- tically meaningful voltage ramp stress (VRS) HCI data. [9] Figure 3 shows the correlation between initial driving current Idsat and VRS HCI. The two groups of “with LDD” and Scheme B are statistically different. The optimized Scheme B shows higher Idsat but better HCI performance, indicating that device performance did not have to be sacrificed to achieve optimal HCI. Another factor affecting HCI degradation is the self- heating effect. Because the discrete fins are surroundedby the gatematerial, the laterally confinedphonon scattering results in higher thermal resistance and heat cannot be dissipated as fast as for a planar CMOS transistor during its operation. There are many factors that could affect the severity of self-heating such as fin height, fin sidewall slope, fin number, and gate arrays. W. Yeh et al. [10] reported that fin numbers showclear correlationwith drain current reduction, which indicates a self-heating related behavior as shown in Fig.4. They pointed out that for circuits composed by clus- tered fins, the local self-heating effect could reduce drain current and transconductance of n-type FinFET devices. However, self-heating did not worsen HCI degradation on the n-type FinFET devices. Their proposedmechanism for this behavior is as follows: Amongmulti-fin FinFET, fins are packed into a small space, causing charges to repel each other and reducing the inversion charges at the center fin. The suppression of impact ionization by this clustered fins effect results in lower hot carrier induced degradation. M. Jin et al. 11] reported that among FinFET transistors, IO p-type field effect transistor (PFET) was actually suf- fering more from the self-heating effect than IO n-type field effect transistor (NFET). The activation energy of IO PFET is much higher than IO NFET, which accelerates the HCI degradation through higher temperature induced by self-heating, as in Fig. 5. Therefore, to correctlymodel the IOPFETHCI degrada- tion, the self-heating effect in the lifetime extrapolation Fig. 2 Impact ionization profile: Original vs. optimized. Fig. 3 VRS HCI correlation to initial Idsat: With LDD vs. Scheme B. (continued on page 34)