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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 4 30 DEVICE RELIABILITY CHALLENGES IN ADVANCED FINFET TECHNOLOGY Xinggong Wan Quality and Reliability Assurance Department GlobalFoundries Inc., Malta, New York xinggong.wan@globalfoundries.com EDFAAO (2019) 4:30-37 1537-0755/$19.00 ©ASM International ® INTRODUCTION The three main degradation mechanisms for CMOS device reliability include hot carrier injection (HCI), bias temperature instability (BTI), and time-dependent dielectric breakdown (TDDB). [1] For planar CMOS devices inparticular, comprehensive researchhas led to thematu- ration of standards and qualification efforts. However, with device dimensions continuously scaling, FinFET and high-kmetal gate (HKMG) have becomemainstreamtech- nology. Fin field-effect transistor (FinFET) offers superior advantages such as reduced short channel effects, good subthreshold swing, and less threshold voltage roll off. Conventional planarMOSFEThas aplanar source-to-drain channel. However, with FinFET, the channel stands up like a fin and the gatematerial wraps around it, which actually makes a channel comprised of a top and two sidewalls, as shown in Fig. 1. Because the silicon surface between the fin top and sidewall are quite different, the carrier mobility, interface traps, and reliability degradation may also be affected. This article will highlight some key reliability challenges with FinFET technology. HOT CARRIER INJECTION HCI is awell-characterized intrinsic degradationmech- anism for CMOS technologies. In general, hot carriers gen- erate impact ionization at the drain end pinch-off region. Electron-hole pairs created by impact ionizationwill form two leakage current paths: Electrons injected into the gate will increase gate leakage current and holes injected into substrate will form substrate current. For conventional planar CMOS devices, the HCI challenge occursmostly on IO n-type field effect transistors (NFETs) because the sup- ply voltage is almost constant to the previous nodes while the device channel length is scaled down aggressively. [2-8] However, in FinFET, there aremany geometric factors that affect HCI, such as fin width, height, and sidewall slope. Whether it is a core device or IO device, once the junction is not optimal, HCI degradation couldworsen andbecome a bottleneck for device qualification. The use of tuning knobs to improve HCI are gener- ally about modifying the source/drain junction profile to achieve lower lateral electrical field (e-field) and reduce impact ionization during device operation. However, there is always a trade-off between reliability and device performance targets such as threshold voltage (V th ) and drive current (Idsat) versus leakage current (Idoff). On conventional planarMOSFETdevices, it iswidely accepted that with the help of technology computer-aided design (TCAD) simulation, one could identify an optimum Fig. 1 FinFET 3D channel feature: Distinct fin sidewall and top. The thin layer marked in black is the interfacial layer (IL), and the pink layer is the high K layer.