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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 4 26 As the layer gets thicker, the topographic profile smooth- ens and this effect dampens, leading to a higher resistance change rate. This results in slope changes of the graph curve in Fig. 5. The resistance deposition process described in this case study, from the baseline resistor deposition to the final resistor deposition, took approximately 45 minutes. This fast pace was due to all the steps being made con- secutively, without having to tilt the sample back and forth between 0° and 54°. Live current monitoring during the resistor deposition also provides a gain in accuracy of the resistance value, whichwould be impossible tomatch if the probes could only be landed at 0° tilt. CASE #2: METAL LINE SHORT LOCALIZATION Localizing shorts in integrated circuits is part of the daily routine of many semiconductor failure analysts as it is the first step before further defect investigation. EBAC imaging for highlighting interconnected networks, and FIB for cutting lines, are premium tools for shorts localization. Figure 7 illustrates the principles of that process. The “green” metal line has an undesirable con- nection with the “red” metal line. A nanoprobe in contact with the first line is used to produce EBAC images of the interconnected lines. To identify if the short is located at a crossing point, the red line is FIB cut close to where it crosses the green line. After the cut, if the inferior fraction of the red line overlapping the green line does not appear in the EBAC image anymore, there is no short between the lines at this location (Result 2). On the contrary, if this fraction remains visible, it means the short is located at this crossing point (Result 1). In this case study, we describe the defect localization of a short on an ASIC from the automotive industry, which was identified to behave abnormally. After electrical char- acterization at the bond pad level, it appeared that one of the signals did not switch correctly and instead kept a constant low. The chip was decapsulated and mounted on a SEM stub using conductive glue. As in the first case study, after identifying the corresponding network on the chip, an opening in the passivation layer was made using the FIB. A contact padwas deposited to gain access to the network via nanoprobing. To produce the EBAC images, the probe connected to the input high of the EBAC amplifier was first landed on the contact pad, while the other probe connected to the input low of the amplifier was placed in contact with the local ground of the circuit. As a matter of comparison, Fig. 8 shows on the left, an image of a functioning device with only one highlighted metal line and, on the right, an image of the failing device with many highlighted lines. This means that not only the suspected network (Signal A) is lighted up, but also another network at a superior Fig. 8 EBAC pictures of the suspected network taken on both a functioning device (left) and failing device (right). An additional network appears on the failing device image. The crossing points of the four networks are indicated. Fig. 7 Schematic of the procedure used to determine if a short is located at a specific crossing point. If the crossing point can still be seen on the EBAC image after the cut, the short location has been identified. FASTER AND MORE ACCURATE FAILURE ANALYSIS (continued from page 24)