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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 4 2 PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Felix Beaudoin Editor/GlobalFoundries; felix.beaudoin@ globalfoundries.com Scott D. Henry Publisher Mary Anne Fleming Manager, Technical Journals Kelly Sukol Production Supervisor Joanne Miller Managing Editor ASSOCIATE EDITORS Nicholas Antoniou Nova Measuring Instruments Navid Asadi University of Florida Guillaume Bascoul CNES France Michael R. Bruce Consultant David L. Burgess Accelerated Analysis Jiann Min Chin Advanced Micro Devices Singapore Edward I. Cole, Jr. Sandia National Labs Szu Huat Goh GlobalFoundries Singapore Martin Keim Mentor, A Siemens Business Ted Kolasa Northrop Grumman Innovation Systems Rose M. Ring Lam Research Sam Subramanian NXP Semiconductors Paiboon Tangyunyong Sandia National Labs David P. Vallett PeakSource Analytical LLC Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is pub- lished quarterly by ASM International ® , 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org.Copyright©2019byASMInternational.Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $150 U.S. per year. Authorizationtophotocopy itemsfor internalorpersonaluse, orthe internalorpersonaluseofspecificclients, isgrantedby ASM Internationalfor librariesandotherusersregisteredwith theCopyrightClearanceCenter(CCC)TransactionalReporting Service, provided that the base fee of $19 per article is paid directlytoCCC,222RosewoodDrive,Danvers,MA01923,USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. D ating back to the 1960s, it was apparent to semiconductor experts that a regular shrinking of electronicswouldoccur and condense increasing functionality onto devices at frequent intervals. By themid 1970s, this process of doubling the density of transistors every two years showed clear trend lines and was termed “Moore’s Law,” after Gordon Moore. While there have been challenges to this law in recent years, the general cadence of new technology development continues at a feverish pace with an increasing number of major semiconductor device and packaging integration changes being realized. As an example of this rapid change, within the past few years we have witnessed the widespread transition from gate-first polysilicon SiO 2 MOSFETs to gate-last high-K metal gates, and to 3D FinFET devices as the standard CMOS logic production transistor. It is forecast that in less than three years from now, the next major transistor integration will reach production—the GAAFET (gate-all-around field-effect transistor). Beyond the transistor integration example, many other innovative technologies advanc- ing the state of electronic device technologywill continue to challenge failure analysts and our current best-known analysis methods. Reviewing failure analysis roadmap publications from the past few decades, common threads appearwith similar discussionpoints andconcerns that remain applicable today. Growing structural and electrical feature count will increase the number of possible failure locations requiring newnavigation and fault isolation techniques. Progressively smaller or thinner defects need to be identified, primarily driven by decreased transistor and interconnect width and feature pitch, but also by the introduction of new material sets. Increasing die size and number of metallization layers results in ever more inspection locations to consider. Generally speaking, these changes result in more demanding resolution, detectability, and precision requirements for inspection, fault isolation, and physical analysis and sample preparation techniques. These challenges have existed for decades and solutions have been real- ized thanks to the creativity of failure analysts, equipment vendors, consortia, and universities. However, recent changes in the semiconductor industry along with further technology development and increased fab costs are reducing the focus on these challenges. Over the last approximately 20 years, the number of companies that own andoperate a bleeding edge CMOS logic fabhas dwindled from>25 to a rather lonely three companies. During the prior time period, these 25 companies most likely had failure analysis teams actively conducting research and NOVEMBER 2019 | VOLUME 21 | ISSUE 4 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL PREPARING FOR THE FUTURE OF FAILURE ANALYSIS Ryan Ross, Jet Propulsion Laboratory, California Institute of Technology ryan.ross@jpl.nasa.gov edfas.org (continued on page 57)