November_EDFA_Digital

edfas.org 1 1 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 4 Table 3 Derived specimen thickness, t, given the measured t/ λ and mean-free path (MFP) value of 174.298 nm [14] for crystalline Si at 300 kV accelerating voltage t/ λ Thickness, t [nm] Si fin 0.11 19.2 Si substrate 0.07 12.2 Table 4 Comparison of milling rates using the concentrated Ar + milling system of Intel FinFET technologies at 700 eV and 10° specimen tilt 14 nm node 10 nm node Fin layer 4.0 nm/min. 3.6 nm/min. Metal layer 3.0 nm/min. 1.8 nm/min. Gate length, 14nmnode = 20 nm [12] Gate pitch, 14nmnode = 70 nm [2] Gate length, 10nmnode = 18 nm [15] Gate pitch, 10nmnode = 54 nm [2] The decreasing gate pitch of future FinFET technolo- gies will make targeting the fin structure challenging. Targeted milling is necessary—from FIB preparation to post-FIB clean-up using Ar + milling. Based on the results described here, FIB preparation of three to five fin struc- tures followed by iterative Ar + milling to target one fin structure results in a specimen thickness of less than the gate length of the device, i.e., <20 nm for the 14 nm node and <18 nm for the 10 nm node. Therefore, specimen preparation that results in a TEM specimen thickness of 12 to 19 nm is adequate to prepare a 10 nm FinFET. Thepost-FIBcleaningmethodologydiscussedhere can be easily integrated into the current FIB preparation and microscopy workflow for failure analysis. Consequently, the turnaround time for high quality TEM imaging and analysis is significantly improved, which is crucial to support FAB production and/or development of new, smaller node geometries. Preparation of 14 nm FinFET TEM specimens was demonstrated, which resulted in high quality specimens for analytical and high-resolution electronmicroscopy analysis. Controlled and targeted Ar + milling using a concentratedbeamcanbe appliednot only for thinning TEM specimens, but also for targeting defects by iterative milling. Reproducible specimen preparation with unmatched quality and exceptional specimen thick- ness of less than 20 nm for imaging and analysis of FinFET structures is possible. REFERENCES 1. M. Lapedus: Semiconductor Engineering, [Online: 2018]. Available: https://semiengineering.com/nodes-vs-node-lets/. 2. M. Bohr: “Leading at the Edge: Intel Technology andManufacturing,” Technology and Manufacturing Day, San Francisco, March 2017. 3. M. Lapedus: Semiconductor Engineering [Online: 2018]. Available: https://semiengineering.com/transistor-options-beyond-3nm/. Fig. 7 EDS elemental maps of the PMOS area of the FinFET specimen after Ar + milling. Fig. 8 Unfiltered image (a) and EELS thickness map (b) of the Ar + milled specimen shown in Fig. 7b. The color is based on the t/ λ scale. Figure reproduced from Reference 11.