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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 4 10 may be FIB-induced damage. The fast Fourier transform acquired from the Si in the fin (Fig. 6a, inset) shows a dif- fused halo in the background, which typically originates froman amorphousmaterial; therefore, the specimen has an amorphous surface following Ga + milling. Conversely, the Ar + milled specimen in Fig. 6b has an amorphous-free surface (Fig. 6b, inset) and clearly shows individual atoms of Si on the fin and amorphous high-k andwork-functionmaterial above the fin. Further, noalter- ation of the FinFET specimen layers after Ar + milling was observed based on the acquired EDS elemental maps (Fig. 7). In effect, thin layers such as the HfO 2 from the FinFET were easily resolved. The thickness of the Ar + milled specimen used for the atomic resolution imaging was determined using EELS. The EFTEM thickness map is a relative-thickness calcu- lated map based on the ratio of the zero-loss map (not shown) and the unfiltered image (Fig. 8a) using the log- ratio method. [13] The relative thickness map is in units of t/ λ , where t is the specimen thickness and λ is the inelastic mean free path of the primary beam electrons through a material at a given accelerating voltage. Figures 8a and b showan unfiltered image and an associated EFTEM thick- ness map of the Ar + milled specimen. Based on the EFTEM map shown in Fig. 8b, dark blue areas are equivalent to t/ λ = 0.25 and are the thinner areas—specifically the Si substrate and at the FinFET structure. The green areas are equivalent to t/ λ = 0.50 and are identified as the metal contact region. The thickness values calculated from the relative t/ λ values, which are based on a value of λ for Si with 300 keV primary elec- trons, are summarized in Table 3. The area of the fins was t/ λ = 0.11, which is 19.2 nm, while the Si substrate was t/ λ = 0.07, which is 12.2 nm. The resulting thickness using targeted Ar + milling surpasses the specimen thickness requirement of 20 to 30 nm for imaging 14 nm FinFET structures. [6] Further, the 19.2 nm measured thickness at the fin is close to the estimated specimen thickness of 20 nm, based on the STEM image in Fig. 2c. OUTLOOK AND CONCLUSION Although this article examines 14 nm FinFET technol- ogy, it is also applicable to the 10 and 7 nm FinFET tech- nologies currently in production. Milling rates for 700 eV post-FIB clean-up of the fin structure with the gate oxide andmetal layers can be estimated (see Table 4) using the reported gate pitch and gate length for both the 14 and 10 nm Intel FinFET devices. Fig. 5 HAADF-STEMimagesofPMOS(top)andNMOS(bottom) regions of a FinFET specimen Ga + milled at 30 kV and then5kV (aandc) followedbyAr + ionmillingat 700eV, 500 eV, and then 300 eV (b and d). Fig. 6 HAADF-STEM image of the fin in the PMOS region from Fig. 5 after Ga + milling (a) and after sequential Ga + and Ar + milling (b). Insets in (a) and (b) are fast Fourier transforms derived fromthe Si in the fin. Figure reproduced from Reference 11. POST-FIB CLEANING OF TEM SPECIMENS (continued from page 8)