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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 3 16 FAILURE ANALYSIS FOR HARDWARE ASSURANCE AND SECURITY M. Tanjidur Rahman and Navid Asadizanjani Department of Electrical and Computer Engineering, University of Florida, Gainesville nasadi@ufl.edu EDFAAO (2019) 3:16-24 1537-0755/$19.00 ©ASM International ® INTRODUCTION Embeddeddevices and internet of things (IoT) technol- ogy have become an indispensable part of modern life. Such advancement in IoT devices requires a state-of-the- art fabrication process. Accordingly, the semiconductor industry has evolved toward a horizontal businessmodel. However, the involvement of third party intellectual property (IP) owners and offshore foundries has raised concerns regarding security and trust. Outsourcing design and fabrication invites vulnerability regarding malicious activities and alterations in integrated circuits (ICs). Becausehardwaregenerates a trustedand secureenviron- ment for privileged software, it is considered the root of trust for any systemon chip (SoC). The entire root of trust is violated if any malicious alteration is detected. Such malicious modification to the structure and function of a chip can be identified as a hardware trojan. Researchers have proposed several electrical-basedmethodologies to detect these types of modifications. However, in recent years, the research community has proposed physical inspection methodologies as an emerging solution to verify and assess the root of trust. Physical inspectionmethods such as reverse engineer- ing, electrical and optical probing, photonic emission analysis, fault injection techniques, and side-channel analysis have been developed to support chip failure analysis (FA) at the post-silicon stage. Access to the physi- cal chip aswell as several FA analysis tools like chippolish- ing, microscopy, probing, focused ion beam (FIB), x-ray imaging, and laser voltage probing are required for the inspectionmethods namedabove. In recent years, FA tools used for physical inspection have experienced significant advancement in facilitating defect localization. Demand for higher yield and faster FA and fault localization at smaller technology nodes also catalyzed the progress and revolution in FA techniques and tools. However, an adver- sary can use these same FA methods and tools to attack a chip and compromise security by exposing assets like sensitive information, intellectual property, firmware, and cryptographic keys. Physical attackmethods are capable of compromising the confidentiality and integrityprovided by modern cryptography and security measures through observation of a chip’s silicon implementation. Methods developed for the economic growth of the semiconduc- tor industry now appear as tools to gain access to assets hidden in modern embedded devices. Identifying assets worth protecting, developing effective countermeasures against physical attacks, and implementing physical inspection methods as trust Fig. 1 Taxonomy of physical inspection/attacks.