May_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 2 54 GUEST COLUMNIST SUPERCONDUCTING ELECTRONICS: A NEW FRONTIER FOR FAILURE ANALYSIS AND RELIABILITY Nancy Missert, Sandia National Laboratories, Albuquerque, New Mexico namisse@sandia.gov A great need existswith regard to addressing increas- ingly complex global challenges using the power of computation, while also recognizing that a single high-performance exascale computer [1] built using stan- dard CMOS technology would consumemanymegawatts of power. This has driven a resurgence of interest in super- conducting electronics. Although concepts for classical superconducting computing have been around for almost 50 years, the cost associated with cooling to 4 K or -269°C is prohibitive. The lack of compact, cryogenicmemory and the relentless success of CMOShas also limited investment in this area to a few research laboratories. The Cryogenic Computing Complexity (C3) program, [2] sponsored by the Intelligence Advanced Research Pro- jects Activity (IARPA), sought to explore the use of super- conducting single flux quantumlogic anda variety of novel cryogenic magnetic memory devices for the next gen- eration of energy-efficient classical supercomputers. The two logic teams led by Northrop Grumman and IBM, and the two memory teams led by Northrop Grumman and Raytheon BBN, pursued different approaches in collaboration with the MIT-Lincoln Laboratory foundry (for logic), HYPRES, and several university partners. Four years of remarkable progress pushed the field of super- conducting electronics far beyond the state of the art when the program began and demonstrated many of the components needed for energy-efficient superconducting processors andcompactmemory cells. The successes real- ized in this program and the potential for future growth led to the inclusion of cryogenic electronics and quantum informationprocessing as an emerging application area in the Beyond Moore focus report for the IEEE International Roadmap for Devices and Systems (IRDS). [3] State-of-the-art superconducting electronics are cur- rently fabricated on 200mm silicon wafers using thin film niobiumconnecting Josephson junction (JJ) switches that couple Nb electrodes through an aluminum-oxide bar- rier. [4] The switching of a JJ generates a single flux quan- tum (SFQ) voltage pulse with a ~ mV amplitude, ~ psec duration, and an energy dissipation of only ~ 10 - 19 J. Circuits are designed to operate at 4 K, where these SFQ pulses travel along nearly lossless superconducting Nb transmission lines, allowing energy efficient, high speed, digital logic basedon thepresence or absence of thepulse. Recent advances in fabrication technology and circuit design have resulted in junction densities of 10 6 /cm 2 . [5] Even though this integration density is several orders of magnitudebelowthat of standardCMOSmicroelectronics, advanced failure analysis (FA) and reliability studies are needed for continued progress. Several of the materials analysis tools developed for Si-based microelectronics can be used to understand defects in superconducting electronics. For example, focused ion beam (FIB) cross-sectioning combined with electron microscopy and phase mapping detected fluo- rine impurities in the active area of single JJs, guiding modification to JJ processing protocols. [6] A more chal- lenging problem is developing failure analysis tools that can locate isolated defects in large circuits designed to operate at 4 K. Cryogenic circuit-scanning tools do not yet exist, so one approach is to interrogate the circuits at ambient temperature using standard FA techniques such as thermally induced voltage alteration (TIVA). Because superconducting circuits contain similar components as Si microelectronics (e.g., multilayer metal traces “FOUR YEARS OF REMARKABLE PROGRESS PUSHED THE FIELD OF SUPERCONDUCTING ELECTRONICS FAR BEYOND THE STATE OF THE ART WHEN THE PROGRAM BEGAN...”