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edfas.org 35 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 2 The grainy texture of the images in these examples can be attributed to noise introduced by the imaging modality. CONCLUSION Currently, the vast majority of common, everyday devices connected to the internet utilize the computing power of an IC. While becoming an integral part of our daily life, the ICs that are embedded in various devices face an increased risk of tampering and intrusion. These attacks range from cloning the original IC for financial in- centives to inserting Trojans in ICs used in critical, security- sensitive applications. Although there have been sev- eral attempts to protect consumers from these threats, the effectiveness of such measures is limited. For exam- ple, acquiring ICs from a trusted provider has become cost prohibitive. Techniques traced back to the principle of RE, which can be employed to address the trust and assurance of COTS chips, are described in this article. Although real- timemonitoring and functional testing are reviewed, their success rate in identifying threats is limited due to the increasing complexity of the IC. The inherent drawbacks of noninvasive techniques can only be overcome by using physical RE techniques that deconstruct the IC layer-by- layer and reconstruct it. Nevertheless, this article argues that in-depth analysis conducted in thismanner requires a well-qualified SME and a substantially longer time period, depending on the node technology employed by the IC. The time spent by an SME to map the logical struc- tures of the IC can be reduced considerably by apply- ing advanced imaging technologies such as the SEM incorporated into image analysis and machine learning techniques. Although it is a step in the right direction, the accuracy and run-time of these algorithms employed in scenarios linked to RE are not compa- rable with what can be observed in other image analysis and machine learning sce- narios. Therefore, taking into account the potential of these approaches for RE—and consequently, hardware trust and assur- ance—further studies should be performed. Finally, it is worth noting that one of the major obstacles for such studies is the lack of data available to researchers to work on these problems. This article paves the way for a broad discussion on this issue and how hardware trust and assurance can benefit greatly from RE. REFERENCES 1. Y. Jin and Y. Makris: “Hardware Trojan Detection using Path Delay Fingerprint,” in HOST 2008: IEEE International WorkshoponHardware- Oriented Security and Trust, p. 51-57. 2. S. Narasimhan, X. Wang, D. Du, R.S. Chakraborty, and S. Bhunia: “TeSR: A Robust Temporal Self-Referencing Approach for Hardware Trojan Detection,” in IEEE International Symposium on Hardware- Oriented Security and Trust, 2011, p. 71-74. 3. R.S. Chakraborty, F. Wolff, S. Paul, C. Papachristou, and S. Bhunia, “MERO: A Statistical Approach for Hardware Trojan Detection,” in Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems, Springer-Verlag, 2009, p. 396-410. 4. M. Tehranipoor and F. Koushanfar: “A Survey of Hardware Trojan Taxonomy and Detection,” IEEE Des. Test Comput., 2009, 27 (1), p. 1-18. 5. F. Courbon, P. Loubet-moundi, J.J.A. Fournier, and A. Tria: “A High Efficiency Hardware Trojan Detection Technique Based on Fast SEM Imaging,” Des. Autom. Test Eur. Conf. Exhib. (DATE), 2015, p. 788-793. 6. C. Bao, D. Forte, and A. Srivastava: “On Reverse Engineering-Based Hardware Trojan Detection,” IEEE Trans. Comput. Des. Integr. Circuits Syst., 2016. 7. N. Asadizanjani, PAINE Workshop, 2018. 8. M. Holler, M. Guizar-Sicairos, E.H. Tsai, R. Dinapoli, E. Miller, O. Bunk, J. Raabe, and G. Aeppli, High-Resolution Nondestructive Three- Dimensional Imaging of Integrated Circuits Nature, 2017, 543 (7645), p. 402. 9. S.P. Frigo, Z.H. Levine, and N.J. Zaluzec, “Submicron Imaging of Buried Integrated Circuit Structures using Scanning Confocal Elec- tron Microscopy. Applied Physics Letters, 2002, 81 (11), p. 2112-2114. 10. E.L. Principe, N. Asadizanjani, D. Forte, M. Tehranipoor, R. Chivas, M. DiBattista, S. Silverman, M. Marsh, N. Piche, and J. Mastovich, “Steps TowardAutomatedDeprocessing of IntegratedCircuits,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2017. 11. S. Blythe, B. Fraboni, S. Lall, H. Ahmed, and U. de Riu, “Layout Reconstruction of Complex Silicon Chips,” IEEE Journal of Solidstate Circuits, 1993, 28 (2), p. 138-145. 12. R. Quijada, R. Dur, J. Pallars, X. Formatj, S. Hidalgo, F. Serra-Graells: “Large-Area Automated Layout Extraction Methodology for Full-IC Reverse Engineering,” Publication pending, 2018. 13. S. Moore: “This Tech Would Have Spotted the Secret Chinese Chip Fig. 5 The metal layer. The two segments (a and b) show delayering defects. (b) (a)