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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 2 32 cloned chips. [15] Although IC camouflaging, especially dummy contact-based IC camouflaging, has been pro- posed to impair the effectiveness of RE, the availability of automated RE along with a golden chip or layout can be helpful in detecting cloned chips through comparing camouflaged cells only. In recent years, advancements in image analysis and machine learning along with developments in SEM and optical imaging have resulted in development of newand more reliable methods for detecting hardware Trojans within ICs and cloned chips. More specifically, application of appropriate image analysis andmachine learning algo- rithms facilitates faster, automated detection of circuit features as well as extraction of high-level functionality. Such a process generally involves image preprocessing, feature extraction, andclassification. Imagepreprocessing influences the accuracy of perceptual feature extraction throughutilizationof noise reduction, edge enhancement, and segmentation. Feature extraction is comprised of image analysis methods to extract salient features in the SEM/optical chip images. Those features are represented as input for machine learning algorithms, e.g., neural network, support vector machine (SVM), or clustering approaches to classifying modifications in functionality or structure. However, to benefit from advances in ma- chine learning, large sets of data that represent the problem space are required to train machine learning algorithms. Certain types of algorithms suchas deep learn- ingmethods require a vast number of data points, usually in the order of millions, to achieve reasonable classifica- tion performance. Possible approaches include develop- ment of a database for counterfeit ICs and hardware Trojans or synthesizing a realistic training dataset from golden chips/layout. [16] However, the runtime of such methods relies on the presence of an RE system operator or complete automation. Over the years, to address the lack of a golden chip/ layout or a sufficiently large training dataset, various avoidance methodologies such as the secure split- test, physically unclonable functions, and lightweight on-chip sensors have been proposed to protect chips. [15] Nonetheless, advancements in methods such as the Tro- jan Scanner [17] tend to point trust and assurance-related studies toward partial RE-based hardware Trojan detec- tion methods. On the other hand, application of fast and automated RE can establish a secure supply chain com- prised of a trustedmanufacturing facility and distribution for security-critical applications. Such improvement offers effective measures for the avoidance of cloned or Trojan- infected chips. PERFORMING REPLACEMENTS AND UPGRADES Automated IC RE can further enable replacement of obsolete technologies and components. With respect to the ability of automated RE to segment, identify, and interpret different properties of IC layouts, it is possible to not only deconstruct the netlist of a device, but recon- struct it as well. By identifying varying components on a layout and comparing them with typical standard cells, the functionality andnetlist of an IC canbe deconstructed. Subsequently, this information can be used either to analyze possible faults in the layout or for reproduction, if the RE device is an obsolete component no longer in distribution. Further, once the functionality is deduced and the netlist is reconstructed, any desired upgrades (such as additional logic or security primitives) can be added. The newly upgraded design and layout will then be ready for fabrication. [18] CHALLENGES OF IC IMAGE ANALYSIS A fundamental barrier to physical RE techniques is the time it takes to acquire and process images of suitable quality. A suitable image is one where the internal struc- tures of the IC can be readily identified, segmented, and extractedas features—becauseanymisclassified structure can cause the entire functionality of the IC to change. Even themost commonly used imagingmodality, i.e., the SEM, requires approximately one month to acquire good quality images of a 1.5 × 1.5 mm IC employing a 130-nm technology node. A detailed list of the time spent acquiring images is presented in Table 1. [17] For each SEM parameter set, Table 1 The time spent acquiring images Scanning speed Field of view resolution Field of view size 500 µm x 500 µm 20 µm x 20 µm 1 usec/pixel 512 × 512 9 sec 1hr 33min 1 usec/pixel 1024 × 1024 18 sec 3 hr 7 min 1 usec/pixel 2048 × 2048 54 sec 9hr 22min 10 usec/pixel 512 × 512 45 sec 7hr 48min 10 usec/pixel 1024 × 1024 3 min 18 sec 1 d 10 hr 10 usec/pixel 2048 × 2048 6 min 25 sec 5 d 12 hr 32 usec/pixel 512 × 512 1 min 30 sec 15 hr 0 sec 32 usec/pixel 1024 × 1024 6 min 30 sec 1 d 21 hr 32 usec/pixel 2048 × 2048 24 min 0 sec 11 d 1 hr 100 usec/pixel 512 × 512 4 min 48 sec 2 d 2 hr 100 usec/pixel 1024 × 1024 18min 54 sec 8 d 4 hr 100 usec/pixel 2048 × 2048 1 hr 11 min 30 d 20 hr