February_EDFA

edfas.org 9 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 1 4. J.A. Waicukauski and E. Lindbloom: “Failure Diagnosis of Structured VLSI,” in IEEE Proc. Design & Test of Computers, Aug. 1989, p. 49-60. 5. S. Venkataraman and S.B. Drummonds: “POIROT: A Logic Fault Diagnosis Tool and Its Applications,” in Proc. Intl. Test Conf. (ITC), 2000, p. 253-262. 6. Y. Huang, W.-T. Cheng, R. Guo; T.-P. Tai, F.-M. Kuo, and Y.-S. Chen: “Scan ChainDiagnosis by Adaptive Signal ProfilingwithManufactur- ing ATPG Patterns,” in Proc. Asian Test Symp., 2009, p. 23-26. 7. R. Desineni, O. Poku, and R.D. Blanton: “A Logic Diagnosis Meth- odology for Improved Localization and Extraction of Accurate Defect Behavior,” IEEE Proc. Intl. Test Conf. (ITC), 2006. 8. Y.-J. Chang, M.-T. Pang, M. Brennan, A. Man, M. Keim, G. Eide, B.Benware,andT.-P.Tai:“ExperienceswithLayout-AwareDiagnosis— A Case Study,” Electronic Device Failure Analysis, May 2010, (12) 2, ASM International. 9. M. Sharma, S. Schwarz, J. Schmerberg, K. Yang, T.-P. Tai, Y.-S. Chen, C.-Y. Chuang, F.-M. Kuo, M. Brennan, J. Yeh, and A. Ma: “Layout-Aware Diagnosis Leads to Efficient and Effective Physical Failure Analysis,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2011. 10. R. D. Blanton, J.T. Chen, R. Desineni, K.N. Dwarakanath, W. Maly, and T.J. Vogels: “Fault Tuples in Diagnosis of Deep-Submicron Circuits,” IEEE Proc. Intl. Test Conf. (ITC), 2001, p. 233-241. 11. E. Amyeen, D. Nayak, and S. Venkataraman: “Improving Precision Using Mixed-Level Fault Diagnosis,” Proc. Intl. Test Conf. (ITC), 2006. 12. M. Sharma, W.-T. Cheng, T.-P. Tai, Y.S. Cheng, W. Hsu, C. Liu, S.M. Reddy, and A. Man: “Faster Defect Localization in Nanometer Technology Based on Defective Cell Diagnosis,” IEEE Proc. Intl. Test Conf. (ITC), 2007, paper 15.3. 13. X. Fan, M. Sharma, W.-T. Cheng, and S.M. Reddy: “Diagnosis of Cell Internal Defects with Multi-Cycle Test Patterns,” Proc. Asian Test Symp., 2012. 14. F. Hapke, M. Reese, J. Rivers, A. Over, V. Ravikumar, W. Redemund, A. Glowatz, J. Schloeffel, and J. Rajski: “Cell-Aware Production Test Results from a 32-nm Notebook Process,” IEEE Proc. Intl. Test Conf. (ITC), 2012, paper 1.1. 15. H. Tang, B. Benware, M. Reese, J. Caroselli, T. Herrmann, F. Hapke, R. Tao, W.-T. Cheng, and M. Sharma: “Diagnosing Cell Internal Defects Using Analog Simulation-based Fault Models,” Proc. Asian Test Symp., 2014. 16. M. Keim, P. Muhmenthaler, H. Tang, M. Sharma, J. Rajski, C. Schuermyer, and B. Benware: “A Rapid Yield Learning FlowBased on Production Integrated Layout-Aware Diagnosis,” in IEEE Proc. Intl. Test Conf. (ITC), 2006, p.1-10. 17. H. Tang, M. Sharma, J. Rajski, M. Keim, and B. Benware: “Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement,” in Proc. European Test Symp., 2007, p. 145-150. 18. M. Sharma, C. Schuermyer, and B. Benware, “Determination of Dominant-Yield-Loss Mechanism with Volume Diagnosis,” in IEEE Design & Test of Computers, 2010, (27) 3, p.54-61. 19. B. Benware, C. Schuermyer, M. Sharma, and T. Hermann: “Deter- miningaFailureRootCauseDistributionfromaPopulationofLayout- Aware Scan Diagnosis Results,” in IEEE Design & Test of Computers, 2012, (29) 1, p. 8-18. 20. W.T. Cheng, Y. Tian, and S.M. Reddy: “Volume Diagnosis DataMining,” in Proc. European Test Symp., 2017, p. 1-10. 21. Y. Pan, A. Chittora, K. Sekar, G.S. Huat, Y.G. Feng, A. Viswanatha, and J. Lam: “Leveraging Root Cause Deconvolution Analysis for Logic Yield Ramping,” in Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2013, p. 602-607. 22. C. Schuermyer, S. Malik, and T. Herrmann, “Identifying Systematic Critical Features using Silicon Diagnosis Data,” in Proc. of Advanced Semiconductor Manufacturing Conf. (ASMC), May 2012, p. 15-17. 23. R.D. Blanton, F. Wang, C. Xue, P.K. Nag, Y. Xue, and X. Li, “DREAMS: DFM Rule Evaluation using Manufactured Silicon,” in IEEE Proc. ICCAD, 2013, p. 99-105. 24. W.C. Tam, O. Poku, and R.D. Blanton, “Systematic Defect Identi- fication through Layout Snippet Clustering,” IEEE Proc. Intl. Test Conf. (ITC), 2010, paper 13.2. 25. W.T. Cheng, et al.: “Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diag- nosis Data,” Proc. Asian Test Symp., 2017. 26. W.C. TamandR.D. Blanton, “Physically-Aware Analysis of Systematic Defects in Integrated Circuits,” IEEE Proc. Intl. Test Conf. (ITC), 2011, paper 4.2. 27. G. Casella and R. Berger: Statistical Inference, 2nd Edition, Duxbury Resource Center, 2001. Theorem 1.2.11a. 28. D.A. Schum: The Evidential Foundations of Probabilistic Reasoning, Northwestern University Press, 1994, p. 49. 29. https://www.forbes.com/sites/bernardmarr/2016/09/30/ what-are-the-top-10-use-cases-for-machine-learning-and-ai/. 30. R.H. Byrd, P. Lu, and J. Nocedal, “A Limited Memory Algorithm for Bound Constrained Optimization,” SIAM Journal on Scientific and Statistical Computing, 16 (5), 1998, p. 1190-1208. 31. M. Mohri, A. Rostamizadeh, and A. Talwalkar, Foundations of Machine Learning, The MIT Press, 2012. ABOUT THE AUTHORS Manish Sharma received a bachelor’s degree in electrical engineering from the Indian Institute of Technology in New Delhi in 1997 and a Ph.D. in electrical and computer engineering from the University of Illinois Urbana-Champaign in 2003. From 2003 to 2004, he worked at Nvidia as a DFT engineer. Since 2004, he has been working with Mentor, a Siemens Business in the area of diagnosis and learning from volume diagnosis results. Currently, Sharma is the engineering manager of the silicon learning group at Mentor. Yan Pan is a product diagnostics engineering manager at GlobalFoundries, Fab 8 inMalta, N.Y. His work covers scan diagnostics, layout analysis and statistical volume diagnosis, and electrical fault isolation for advanced technologies at Fab 8. In addition, he leads an effort at Fab 8 to develop volume data analysis infrastructure to identify and resolve systematic yield issues using fab process, test, yield, and product design data. Pan received his Ph.D. in computer engineer- ing from Northwestern University, Evanston, Ill., in 2011 and his M.S. degree in the same field from the National University of Singapore in 2006. He holds three patents and has published more than 20 papers from his work at Northwestern and GlobalFoundries.

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