February_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 1 6 goes through two metal layers M2 and M3, then opens on these layers become diagnosis suspects. Further, if the net is physically close to the net driven by c1 in the M2 layer, then a M2 Bridge between the two nets also becomes a diagnosis suspect, and so on. Finally, the fault f1 can also be associatedwith a defect inside theOR cell c2. However, because the design of the internal implementation of the cells is unknown in this logic model, diagnosis can only point to the entire cell c2 as a suspect. CELL-AWARE DIAGNOSIS LOCATES DEFECTS INSIDE CELLS For diagnosis to further resolve defects inside the cell boundary, it would need to know about the internal workings of the cell. This information can be provided to diagnosis via logical models of all likely defects inside a cell, for all cell types in a design. From the cell’s physical layout, a detailed parasitic SPICE (simulation program with integratedcircuit emphasis) analog simulationmodel is extracted. Also from the cell layout, we can extract the likely locations of defects inside this cell—bridges where two nets come physically close to each other and open in various net segments. Then, for each such defect, the SPICEmodel of the cell is altered to create a defective cell model. Finally, this defective cell model is exhaustively simulatedusingaSPICEanalog simulator and the voltages at the cell outputs are interpreted to create a logical truth table model of the cell. Consider the OR cell in the design in Fig. 1. A layout of this cell is shown in Fig. 3, which also shows two example defects, aMetal1 short between ‘VSS’ and the net ‘2,’ and a poly open between the input ‘A’ and the gate of the PMOS transistor that it drives. The defective cell models for these twodefects are shown in the transistor-level schematics in Fig. 4. Figure 4 also shows howa truth tablemodel for this defect can be constructed by analog simulating various input combinations. As an example, when A=0 and B=0, the bridge causes the output to go from 0 to 1. All other input combinations will not detect the bridge because at least one of theNMOS transistorswill beON, thus shorting the bridge. So, the defect model for Metal1 Bridge-1 will contain only one failing condition ‘A B=00.’ Similarly, logic models are constructed for all potential defects in the cell. Going back to the defective die example in Fig. 2, the logic defect models constructed above can be used to simulate cell-internal defects and check whether the simulated failure response matches the failing test response. For example, simulating the Metal1 Bridge-1 in OR cell c2 will produce a response matching the test failure because the inputs to c2, ‘00’ will cause the output to change from 0 to 1, and this change will be captured in the bottom two flops in the scan chain. This is how diag- nosis becomes cell-aware and reports specific physical defect suspects inside the cell rather than in the entire cell. For our failing die in Fig. 2, the diagnosis result will include several suspects—M2, M3, and V2 opens on the net driven by OR cell c2, anM2 bridge between nets driven by c2 and c1, and aMetal1 bridge inside theOR cell c2. These suspects are equally possible under the infor- mation available from the single failing test pattern, and we do not know which suspect is the real defect in the die. In real defective die there can be more than one failing pattern, which canweed out some of the fake suspects. But in most cases there are still equivalencies that cannot be overcome simply based on Fig. 3 A layout of the OR cell showing two example defects. Fig. 4 Defective cell models for a bridge and open defect.