February_EDFA_Digital

edfas.org 5 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 1 For digital logic, one particularly effective way of identifying the underlying problems leading to yield loss is to build a defect mechanism Pareto chart for a volume of failing die based on scan test diagnosis results. Diagnosis employs simulation analysis to determine a set of potential defects (also called diagnosis suspects) from the failure log of a defective die. Typically, due to logical and electrical equivalencies, the size of this set of diagnosis suspects is greater than one. Therefore, in addition to including the real defect, the diagnosis results may also contain a number of fake suspects. This ambi- guity, or diagnosis noise, makes the building of a defect Pareto chart from volume diagnosis reports a nontrivial task. Root cause deconvolution (RCD) is a technique that can perform this task by using an unsupervised machine learning algorithm to estimate the defect Pareto diagram from volume diagnosis results in the presence of noise. So, combining all of these techniques creates amethodol- ogy that starts with volume diagnosis results, uses RCD analysis to build a defect Pareto chart, and uses this data to select die for FA that most likely represent the defect mechanisms of interest in this chart. For established technology nodes, this methodol- ogy has successfully reduced overall cost and cycle time for finding the root cause of back-end yield loss in the interconnect. Until now, RCD has been limited to interconnect because diagnosis itself was restricted to resolving only interconnect defects. For defects inside the cell, all diagnosis could determine was the defective cell instance rather than the exact physical defect (e.g., Metal1 short). Now there is a new diagnosis technology, called cell-aware diagnosis that allows diagnosis to go down the cell boundary and report suspects inside the cells. Combining volume cell-aware diagnosis results with RCD creates a defect Pareto chart that includes both back-end interconnect and front-end cell-internal physical defect mechanisms. SCAN-BASED TEST FAILURE DIAGNOSIS Most digital logic circuits get tested today by scan- based structural test patterns (Fig. 1). One very important advantage of scan-based testing is that when the test fails, the failing test responses can be used to run automatic diagnosis to determine a set of suspect defect locations that may be causing the test to fail. Finding defect locations is achieved by using two abstractions: 1. A logic-level netlist of the design, in which library cells are interconnected through wires or nets (see example in Fig. 1). 2. A stuck-at fault model, which says that a physical defect manifests itself in the logic-level model of a design by making a particular cell output or input register a fixed 1 or 0 value. The following example illustrates the basic concepts of diagnosis. Again, consider the design in Fig. 1, and this time assume that for a defect the test response is ‘001’ instead of ‘010’ as shown in Fig. 2. Figure 2 also shows that the fault f1 (output of c2 stuck-at-1) can explain the failing test response, therefore diagnosis will correlate this with the physical layout of the net driven by c2 as well as its physical neighbors to come up with diagnosis suspects. For example, if this net Fig. 1 Example design illustrating scan-based test. Fig. 2 Example of failing test response and fault simulation.