February_EDFA_Digital

edfas.org 41 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 1 damage around the capacitors to be exposed was also discussed. Themodule tobe etched is placedonahotplate and heated to ~120°C. A follow-up question was raised about the overmold material type. Mechanical milling was suggested as the first approach for any FA engineer in the labs. The moderator also provided a solution for a scenario where the sample has a leakage fail. Wires can be soldered to the failing trace pins and the sample can bemechanicallymilled (along the perimeter of the failing capacitors) with the cables connected to a parametric analyzer. IV curve will produce a jitter as the milling gets closer to the failing capacitors. The second topic was the method of thinning silicon to less than a micron (submicron polishing). Points of discussion included thermomechanical and edge issues when it comes to uniformity. What would be the chal- lenges and workaround with a very high success rate? A follow-up question was put forth from the audience asking about dimensions of the thinned region. It was also pointed out that submicron thinning would be very risky and not advisable on RMAs. Global thinning is possible but with a low success rate. Thermal components would come into play and this is a continued challenge faced by Intel. PFIB with localized thinning would be the best methodology for a submicron solution. The moderator showed the “orange peel” issue that can come into play when thinning silicon backside below a certain thickness (<10 µm). The interference pattern is due to the shrinkage of the UF and Si causing the orange peel effect. Amember from the audience suggested the use of XeF 2 for localized etching of the silicon backside. Steve Herschbein from GlobalFoundries supported this suggestion by pointing out he has used thismethodology successfully for etching to the TSVs. Another member of the audience pointed out that XeF 2 would be a good approach to localized thinning. The only anticipated bottleneck is the surface profile. NIR laser ablation was suggested as one of the techniques to address this, but the presenter of this technique—who had a paper at ISTFA—pointed out it can only be used for mold compound removal today. The 532 nm laser could potentially be used, but it has not been tried yet. The third topic includedmethods for site-specific cross sectioning for scanning spreading resistance microscopy (SSRM). Any ideas for quick sample prep? If using DBFIB or PFIB, what are the pros and cons? One suggestion was to mechanically polish and then use FIB to clean up the cross section. Luci Sheridan asked how to remove Ga implantation. The difficulty with the FIB technique is at an SRAM array, the atomic force microscopy (AFM) probe needs to land and scan without damaging the Si and it should be free of external ion implantation. A member from the audience suggested LatticeGear can be used to cleave the sample with precision. Sheridan followed up with a question that the cleaved location would require a metal coating to ground the areas to be probedwith AFM. Another suggestion from the audience was to use PFIB. He mentioned that Intel uses PFIB for all nanoprobing applications. Sheridan asked about the VT shift. The reply was less than 5%. Satish Kodali from GlobalFoundries suggested the argon mill with surface touchup. Bevel the top and then cross section to the location using the PFIB. The moderator then quoted an approach from an ISTFA paper 10 years back; cleave the device close to ~20 µm from the site of interest. Use the DBFIB to mill closer to the site of interest and then finish it off with mechanical cross section polishing. The final discussion area considered methods for silicon backside thinning of large dies (25 x 25 mm) while keeping the silicon thickness uniform from the edge to the center. How canwe evenly thin the silicon to ~5 µmall theway across? This was a question put forth by Christian Schmidt, NVidia. Using the CNC approach was one of the replies from the audience. Custom fixtures around the edges of the silicon address the thickness variation due to sample warpage. One suggestion was to solder the sample onto a board if possible, as this would reduce the warpage. The last thought was to run the sample to a high temperature (70⁰-140⁰C) inorder to relax the sample forces and stresses during the thinning process. To increase discussions among the three user group forums this year, the organizers spent an enormous effort preparing for a verbal style format vs. the prior paper presentation style. This increased participation, got the problems and issues out in the open, and stimulated a robust discussion. Networking was achieved by ensuring an in-depth list of topics were raised, thus enabling all users to observe who might provide extra insight, even after the forumwas over. Finally, to keep communication flowing after the user group sessions wrapped up, a new online user group site was set up with the moderators. This new system allows users to post issues and have the moderator help answer questions by steering them to the best resources throughout the niche industry we belong to. We registered roughly 300 users who now plan to use the system between the annual conferences. The new online community is available on ASM Connect located through your My ASMProfile on the ASMwebsite. As orga- nizers of the onsite user groups, we were thrilled with the attendance, robust conversations, and new discussion style format this year.