February_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 1 36 ISTFA 2018 PANEL DISCUSSION A SUMMARY OF THE ISTFA 2018 PANEL DISCUSSION: FAILURES WORTH ANALYZING Susan X. Li* and Renee Parente,** ISTFA 2018 Panel Discussion Organizers *Cypress Semiconductor Corp., San Jose, Calif. — susan.li@cypress.com **Advanced Micro Devices, Austin, Texas — renee.parente@amd.com Invited Panelists: Charles Odegard, Chetan Kumar, Eckhard Langer, Lihong Cao and Nebojsa Jankovic A s a failure analyst, you likely run through the question, “Is this failure worth analyzing?” before you even start working on a case. The 2018 ISTFA panel discussed the types of failures we need to spend time and effort fully analyzing, which types we can use electrical failure mode signature analysis to close, what types requireminimum time and effort, and how to avoid undesirable consequences of analysis. We invited experts fromelectronic semiconductor companies,medical device companies, and subcontracted foundry fab and assembly manufacturers to participate in this year’s panel discus- sion. Our panelists avidly spokewith the ISTFA conference attendees in Phoenix on this interesting topic and shared their insights and perspectives with an enthusiastic audience. This year, we were very fortunate to bring in five expe- rienced panelists from four different industries. Eckhard Langer is a seniormanager responsible for the GlobalFoundries material and physical failure analysis, reliability and electrical characterization, and chemical analysis laboratories. He has beenmanaging failure analy- sis labs in semiconductorwafer fabs formore than20 years and has a wealth of knowledge on product development and customer support from a wafer fab manufacturing standpoint. Charles Odegard is a senior member of the technical staff in the semiconductor quality department at Texas Instruments (TI) and serves as a member of the auto- motive quality “Red Team.” This select group of subject matter experts is called upon to investigate root causes of failure and to drive infrastructure changes that improve quality throughout TI. They also tackle issues fromwafer fab, probe, package assembly, reliability test, and cus- tomer returns. Lihong Cao is a director at ASE Group, responsible for new packaging technology development, technol- ogy promotion, new product introduction, technical program management, strategic planning, and business engagement. Cao is an expert on assembly manufactur- ing processes, with nearly 20 years of experience working on customer support and packaging development for a variety of semiconductor products. Nebojsa Jankovic is the manager of failure analysis innovation at NXPSemiconductors. His programdevelops new tools and techniques along with determining the scope and role of all NXP failure analysis labs. He helped established the expertise center for NXP’s failure analysis in Nijmegen, the Netherlands. Jankovic has also trained numerous failure analysts to become experts in silicon debug and yield analysis. He strongly believes that it is “the FA engineering expertise and experience (collective The panel discussion featured a new open format this year.