February_EDFA_Digital

edfas.org 19 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 1 7. T. Sridhar and J.P. Hayes: “Design of Easily Testable Bit-Sliced Systems,” IEEE Trans. Circuits Syst., Nov. 1981, 28 (11), p. 1046-1058. 8. R.D. Blanton and J.P. Hayes: “Testability of Convergent Tree Circuits,” IEEE Trans. on Comput., Aug. 1996, 45 (8), p. 950-0963. 9. H. Elhuni, A. Vergis, and L. Kinney: “C-Testability of Two-Dimensional Iterative Arrays,” IEEE Trans. CAD, Oct. 1986, 5 (4), p. 573-581. 10. D. Sciuto and F. Lombardi: “New Conditions for Testability of Two- Dimensional Bilateral Arrays,” Systolic Arrays, 1988, p. 495-504. 11. X.T. Chen, et al.: “Novel Approaches for Fault Detection in Two- Dimensional Combinational Arrays,” Defect and Fault Tolerance in VLSI Systems, 2001, p. 161-169. 12. W. Cheng-Wen and P.R. Cappello: “Easily Testable Iterative Logic Arrays,” IEEE Trans. Comput., May 1990, 39 (5), p. 640-652. 13. F. Brglez, D. Bryan, and K. Kozminski: “Combinational Profiles of Sequential Benchmark Circuits,” Int. Symp. Circuits and Syst., 1989. 14. S. Davidson: “ITC’99 Benchmark Circuits-Preliminary Results,” IEEE Proc. Int. Test Conf., 1999, p. 1125-1130. 15. P. Fynan, Z. Liu, B. Niewenhuis, S. Mittal, M. Strojwas, and R.D. Blanton: “LogicCharacterizationVehicleDesignReflection via Layout Rewiring,” in IEEE Proc. Int. Test Conf. (ITC), Nov. 2016. 16. Z. Liu, P. Fynan, and R.D. Blanton: “Front-End Layout Reflection for Test Chip Design,” in IEEE Proc. Int. Test Conf. (ITC), 2017, p. 1-10. 17. Z. Liu and R.D. Blanton: “Back-End Layout Reflection for Test Chip Design,” in IEEE Int. Conf. on Computer Design, Oct. 2018. 18. M. Grant and S. Boyd: “CVX: Matlab Software for Disciplined Convex Programming,” Version 2.0, beta. http://cvxr.com/cvx, Sept. 2013. 19. N.V. Sahinidis: “BARON 18.5.9: Global Optimation of Mixed-Integer Nonlinear Programs,” User Manual, 2018. ABOUT THE AUTHORS Zeye Liu earned B.S. and M.S. degrees in electronics engineering from Xi’an Jiaotong University, China, in 2008 and 2011, respectively. He worked at Marvell Technology Group as a senior DFT engi- neer from2011 to 2015. He is currently pursuing a Ph.D. in electrical and computer engineering from Carnegie Mellon University (CMU). He was the recipient of the best paper award at the ACM Great Lakes Symposium on VLSI in 2017. His research interests include integrated circuit testing, machine learning hardware implementation, and hardware security. Ben Niewenhuis received his B.S.E. from Calvin College in 2012 and Ph.D. from CMU in 2018 in electrical and computer engineering, and he was the recipient of the IBM SRC Robert H. Dennard Fellowship. He is currently employed as a digital design engineer with Texas Instruments. His research interests include faultmodels for digital integrated circuits, test chipdesign, design-for-testability, and hardware security. Soumya Mittal received a B.Tech. degree in electronics and communication engineering from the Indian Institute of Technology Roorkee in 2014. He is currently pursuing a Ph.D. in electrical and computer engineering from CMU. He held an internship at GlobalFoundries and Intel Corp. in the summers of 2015 and 2016. His research interests include integrated circuit testing, defect modeling and diagnosis, and application of machine learning to test failure data. Phillip Fynan received his B.S. degree in electrical engineering from Calvin College and his M.S. degree in electrical engineering fromCMU. During graduate school, his research focused on applyingmachine learning to reliability andmanufacturability, aswell as novel algorithms for test chip design. Fynan is currently an engineer at Marvell Semiconductor, having been theremore than a year, and works in DFT for networking products. Shawn Blanton earned a B.S. degree in engineering from Calvin College in 1995, an M.S. degree in electrical engineering from the University of Arizona in 1989, and a Ph.D. in computer science and engineering fromthe University of Michigan in 1995. He is currently a professor in the department of electrical and computer engineering at CMU. Blanton has served as the director of the Center for Silicon System Implementation (2008-2014), associate director of the SYSU-CMU Joint Institute of Engineering (2015-2017), and now serves as director of diversity for the college of engineering at CMU. His research includes test and diagnosis of integrated circuits, silicon security, and hardware acceleration of machine learning within integrated systems.