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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 1 18 the templates produced by the solvers, (e.g., the inv000 standard cell in Fig. 4b). In order to achieve minimal, overall design reflection error, the solver must use FUB implementations that overuse certain standard cells. Both of these difficulties can bemitigated by increasing the size and diversity of the FUB library. Standard cell incorporation is not the only objective for a CM-LCV design. Table 3 further illustrates the testability advantages of the CM-LCV. The first two rows present the collective test characteristics for all of the benchmark circuits fromthe International Conference on Circuits and Systems (ISCAS89) [13] and all of the benchmark circuits from the International Test Conference (ITC99) [14] with respect to the SSL and IP fault models. The third row describes a CM-LCV design constructed from a six-input and six-output FUB function with the sole objective of maximizing fault coverage. The CM-LCV achieves similar or better SSL and IP fault coverages with a significant reduction in the number of tests. Table 4 shows the results when IP fault coverage and IP fault classes are included as objectives. The first two rows show the IP fault characteristics for the ISCAS89 and ITC99 benchmark circuit families, as well as the number of tests required. The three CM-LCV rows show the same properties for three different templates optimized to incorporate the standard cell usages in the ISCAS89 design family, each with a different trade-off between the two objectives of minimizing the standard cell incorporation error and achieving high IP fault coverage. The number of redundant IP fault classes is maintained at zero for all CM-LCV designs. Adding these objectives to the optimiza- tion problemdoes negatively impact the design reflection error. However, this canbe controlledby adjustingweights in the solver to achieve the desired balance between the two objectives. CONCLUSION Anewproduct-like test chipcalled theCM-LCVhasbeen introduced to address the challenges facing conventional product-like test chips. The CM-LCV implements a highly testable two-dimensional array of FUBs that reflects the properties of product designs, resulting in an optimized test chip for yield learning. Experimental results show that the CM-LCV can be rigorously testedwith a small, constant number of tests while simultaneously achieving SSL and IP fault coverages that are comparable to or better than those achieved using benchmark designs. The CM-LCV reflects customer designs by matching the standard cell usage frequencies with design reflection error values ranging between 0.24% and 22.0%. Future work will focus on improving the design reflec- tion process, both through reducing the standard cell design reflection error and including additional metrics, as well as performing diagnosis experiments on data col- lected fromfabricated and tested instances of the CM-LCV. REFERENCES 1. K.Y Cho, S. Mitra, and E. McCluskey: “Gate Exhaustive Testing,” in IEEE Proc. Int. Test Conf. (ITC), 2005. 2. R.D. Blanton, B. Niewenhuis, and C. Taylor: “Logic Characterization VehicleDesign forMaximal InformationExtraction for YieldLearning,” in IEEE Proc. Int. Test Conf. (ITC), 2014. 3. B. Niewenhuis andR.D. Blanton: “Efficient Built-inSelf Test of Regular Logic CharacterizationVehicles,” VLSITestSymposium(VTS),2015IEEE 33rd, Napa, CA, 2015, p. 1-6. 4. R.D. Blanton, B. Niewenhuis, and Z.D. Liu: “Design Reflection for Optimal Test-Chip Implementation,” IEEE Proc. Int. Test Conf. (ITC), 2015, p. 1-10. 5. A.D. Friedman: “Easily Testable Iterative Systems,” IEEE Trans. Comput., Dec. 1973, C-22 (12), p. 1061-1064. 6. R.D. Blanton and J.P. Hayes: “Properties of the Input Pattern Fault Model,” IEEE Int. Conf. on Computer Design (ICCD), 1997, p. 372-380. Circuit SSL fault IP fault Coverage No. of Tests Coverage No. of Tests ISCAS89 99.5% 584 89.1% 1336 ITC99 99.0% 5026 72.6% 10583 CM-LCV 99.4% 64 92.4% 64 Table 3 SSL and IP fault coverage comparison for the CM-LCV against various design families Table 4 Fault coverage results for benchmark design families and CM-LCV Circuit Redundant IP faults Total IP faults IP fault coverage Standard-cell incorporation error Redundant IP fault classes Tests ISCAS89 1220 114318 89.1% NA 2 1336 ITC99 398687 1426604 72.6% NA 0 10583 CM-LCV1 8484 72254 88.3% 22.0% 0 64 CM-LCV2 15054 89486 83.3% 18.5% 0 64 CM-LCV3 21179 98750 78.5% 14.8% 0 64