February_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 1 16 achieves the given objectives. This FUB template can then be instantiated any number of times to construct an array of arbitrary size that maintains the desired design and testability properties. PHYSICAL PROPERTIES IMPLEMENTATION The CM-LCV is designed for maximal testability and diagnosibility while being sensitive to the defect mecha- nisms that affect product designs. It is basedon the insight that the manufacturing process is sensitive only to the physical features of a design (i.e., its physical layout), and not the logic functionality the layout implements. Thus, given the FUB template with high defect transparency, different physical implementation flows can be applied to incorporate the layout features of interest. Particularly, the design flow of Fig. 3 creates a FUB template that minimizes the difference between the target and CM-LCV standard-cell usage frequencies. The physical properties within the standard cells (e.g., arrangement of transistors, contacts, and intra-cell interconnects) will be exhibited in the physical design of the FUB template that is created using a commercial place-and-route flow. Further, work presented at the International Test Conference in 2016 [15] AN AUTOMATED METHODOLOGY FOR LOGIC CHARACTERIZATION VEHICLE DESIGN (continued from page 14) preserves all the front-end physical characteristics (e.g., standard cell neighborhoods) found in customer prod- ucts through rewiring either the entire layout or some portion of it. Rewiring eliminates all the existing intercon- nects of a customer design, then reroutes the already- placed standard cells into an LCV. Thus, the standard cell neighborhood for a target design is completely and comprehensively preserved. In addition, other work [16,17] has investigated implementing the FUB template that incorporates either the front-end or the back-end layout geometries of interest while ensuring defect transparency. EXPERIMENTS This section describes the results of several CM-LCV design runs. Table 1 depicts the design and test char- acteristics for various FUB array sizes for a four-input and four-output FUB, and illustrates the advantage of C-testability. C-testability achieves the same SSL fault coverage with fewer test vectors and less CPU time for test-set generation compared to conventional automatic test pattern generation (ATPG) tools. Given the testability advantages of the CM-LCV, the more challenging task for the CM-LCV is standard cell incorporation. The goal of standard cell incorpora- tion is to establish the same cell distribution charac- teristics derived from a design or family of designs within an LCV implementation. The design flow of Fig. 3 is applied to five standard cell distributions extracted from industrial designs. Two approaches are used to solve the matrix formulation created for the five industrial designs, namely convex and mixed-integer nonlinear. Specifically, a convex solver is available via CVX Research, [18] while the mixed-integer nonlinear program approach is avail- able in BARON. [19] Table 2 provides a detailed analysis of the standard-cell usage results for CM-LCVs constructed Table 1 The CM-LCV design and test characteristics for achieving 100%SSL fault coverage for various array sizes Array size No. of gates No. of SSL faults ATPG Constant test No. of tests Time (sec) No. of tests Time (sec) 10×10 1860 9680 20 0.01 16 0.12 25×25 11025 58700 29 0.16 16 0.13 50×50 43.3K 232.4K 32 2.4 16 0.12 100×100 171.6K 924.8K 37 53.7 16 0.15 250×250 1.1M 5.762M 42 2046 16 0.20 500×500 4.3M 23.0M 46 >18000 16 0.22 Table 2 Detailed standard cell incorporation results for the CM-LCV for various objectives Circuit example Block C Block D Block G Block I Block U No. of logic functions 48 52 53 54 45 No. of standard- cell types 4,582 3,686 3,901 4,394 2,903 No. of standard cells 80,465 83,708 89,096 74,469 69,787 Solver Err. FT RT Err. FT RT Err. FT RT Err. FT RT Err. FT RT BARON 0.6% 1,564 53,665s 2.7% 2,112 33,114s 5.8% 2,006 28,396s 6.7% 1,886 33,785s 0.1% 1,330 51,192s Convex 3.3% 1,604 12.6s 5.7% 2,127 13.1s 6.5% 2,046 26.2s 7.4% 1,898 19.7s 3.2% 1,339 13.4s